Hi All, Below is the draft proposal for SBI Debug Console Extension. Please review it and provide feedback. Thanks, Anup Debug Console Extension (EID #0x4442434E "DBCN") ==============================

That is because it is useful to have debug console output when porting a hypervisor or baremetal code to a new board. Of course, if a hypervisor is already available for the board, then it would be ju

Hi Anup, Here are my thoughts: * Guest memory access: I think this would be the first SBI extension to require access to guest memory. This needs to be considered carefully, but I think the higher ban

It's also helpful in early board bringup and early debugging as pointed out by Heiko as well. To address some of the concerns raised above, how about putting some restrictions on sbi_debug_console_set

Thanks, it will be nice to drop putchar. What is the motivation for `area_offset`? Will the supervisor use different offsets for different harts? What are the advantages and disadvantages of the offse

Hi All, My apologies for the long email up front. I hope people find this useful as well as a starting point for a broader discussion in how all these pieces fit together within RISC-V. There are impl

All, As per the policy governing chairs and vice chairs, we are holding a call for candidates for the positions of CHAIR and VICE-CHAIR for the OS-A SEE TG. To nominate yourself or another member of t

Hi All, I am pleased to inform that 45 days of public review period has ended for the RISC-V UEFI Protocol Spec. Feedbacks during review period are addressed. We will go through the remaining process

Hi All, I'm cross posting to tech-unixplatformspec@ and tech-os-a-see@ lists because there wasn't sufficient overlap in membership to get the proper visibility. I had proposed a charter that can be fo

Hi, I have some questions related to the Watchdog spec found here: https://github.com/riscv-non-isa/riscv-watchdog/blob/main/riscv-watchdog.adoc 1. The spec goes to great lengths to describe the watch

I haven't been following the H extension closely, and was not aware the HBI/HEE terms have suffered the same fate. This is one of those things that makes it hard to convince people to take RISC-V seri

Add requirement for preserving the PCIe ID routing as described in issue: https://github.com/riscv/riscv-platform-specs/issues/81 Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec

Currently the SBI specification defines how to hand device-trees from the SEE to the S-mode firmware. In the context of Trusted Firmware A a document has been developed describing what a more generic

Hi All, The next platform HSC meeting is scheduled on Mon Apr 4th 2022 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki

UEFI uses to talk of configuration tables not of firmware tables. Add missing 'the', 'and'. Enhance readability of sentence concerning ExitBootServices(). Signed-off-by: Heinrich Schuchardt <heinrich.

This is to announce the start of the public review period for the RISC-V UEFI Protocol specification. This specification is considered as frozen now as per the RISC-V International policies. The revie

Hi All, Due to lack of a full agenda, I am canceling the next platform HSC meeting on Monday Mar 21st 2022. This way, people can use this time to attend other RISC-V meetings. In terms of the discussi

Hi All, I wanted to point out that we have GitHub repositories and a mailing list for OS-A SEE (Supervisor Execution Environment) TG. Please join if you are interested. GitHub Admin: https://github.co

Hi All, The next platform HSC meeting is scheduled on Mon Mar 7th 2022 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki

Is it expected that there should be a watchdog timer and timeout signal per hart in the system, or is okay for there to be one timer in the system and for the timeout signal to be delivered to a speci