RISC-V UEFI systems need to support new RISCV_BOOT_PROTOCOL. This protocol is required to communicate the boot hart ID from firmware to the bootloader/kernel. This protocol specification is maintained

Hi all! I just sent this to tech-chairs, but due to the nature of your work Stephano suggested getting feedback here as well. The Configuration Structure task group has been working on how software ca

I just realized that the below email was not delivered to unix platform mailing list and linux-riscv mailing list because of the attachment. Reseeding it again without the attachment. Apologies for th

Hi All, I submitted a pull request to the platform spec repo: https://github.com/riscv/riscv-platform-specs/pull/75 This is definitely a WIP, but I wanted to start the conversation. Much of the langua

Hi All, During the Platform HSC the topic of specifying an expected cache granule size for a platform was brought up. Below are some thoughts/observations on the topic. The purpose of this email is to

All, Recently a PR was sent out to remove U and VU mode standardization from the platform spec scope. Which is sort of right and sort of wrong. I brought this issue up with Krste and Andrew (especiall

Hi All, The next platform HSC meeting is scheduled on Mon Jan 24th 2022 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki

Signed-off-by: Paul Donahue <pdonahue@...> --- riscv-platform-spec.adoc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc index 23

Hi All, As we discussed in the Platform HSC meeting today, here is the document which details a new RISC-V specific EFI protocol. https://github.com/riscv-non-isa/riscv-uefi/releases/download/0.1/EFI_

Hi there, In the OS-A platform spec I see the following requirement: • dcsr.stopcount and dcsr.stoptime must be supported and the reset value of each must be 1 ◦ Rationale: The architecture has strict

As discussed on the mailing list: - 4.7.3.4 - Fixed typo - Added clarification for requests with NS=1, RO=0 - 4.7.3.5 - Added topology depicting a RP, RCiEP, RCEC on the root bus - Removed constraint

Hi All, The next platform HSC meeting is scheduled on Mon Jan 10th 2022 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki

Hello, I’m new to participating in the platform WG. I’m working at SiFive now. I spent the last 20 years doing PCIe compliant IO fabrics for Intel chipsets. I have a few comments / questions about the

Greetings All! Please help with the following questions about the OS-A/server extension: Section 2.1.4.1 - Timer support: Should the ACLINT MTIMER support should be optional or moved into the M-platfo

RISC-V SBI provides platform agnostic functions for kernels. The nomal handling procedure in an SBI implementation would include context switch and call higher language code, e.g. Rust or C code. Howe

As per the discussion and agreement during the Platform HSC meeting, this patch splits the content of the platform spec into 3 different sections - an OS-A Common Requirements section, OS-A Embedded P

Hi All, The next platform HSC meeting is scheduled on Mon Dec 13th 2021 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki

Hi All, As we discussed during the platform HSC meeting yesterday (Nov 29, 2021), we are calling on volunteers to own and drive the improvement of the definitions/terms used in the platform spec. Plea

Some of the ISA requirement sections do not belong to a platform specification and can move to the profile specification. The fence.i recommendation belong to software section as it talks about a requ

Hi All, The next platform HSC meeting is scheduled on Mon Nov 29th 2021 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki