RISC-V SBI provides an interface via enironment call to provide platform agnostic features, which is similiar to operating system's syscalls. According to current SBI specification, this environment c

Last level cache and NUMA node cache events are not specific to per hart. Do not make them mandatory for per hart performance monitor events. Signed-off-by: Atish Patra <atishp@...> --- riscv-platform

The platform spec provides various choices for interrupt controller to be implemented in the platform. As M-mode is not a mandatory requirement any more and VS-mode is only required for platforms with

Hi, The RISC-V international has recently established a ratification policy[1] for non-ISA specification as well. All of the non-ISA specifications (e.g SBI, psABI, ACLINT) will have to go through the

As per the discussion in the mailing list, M-mode requirements should not be included in this version of the platform specification to allow platform vendors more flexibility in implementing privilege

Signed-off-by: Atish Patra <atishp@...> --- riscv-platform-spec.adoc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc index 0

This version of the platform specification doesn't mandate M-mode requirements. However, it should specify M-mode access protection from lower privilege modes for platforms that do implement M-mode. O

+ platforms mailing list Regards Kumar

Hi All, During our Platform HSC meeting today, one of the topics that came up for discussion was whether we should mandate the 16550 UART for all OS-A platforms and keep this requirement within the “C

Hi All, The next platform HSC meeting is scheduled on Mon Nov 15th 2021 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki

As per the discussion in the mailing list, M-mode requirements should not be included in this version of the platform specification to allow platform vendors more flexibility in implementing privilege

This version of the platform specification doesn't mandate M-mode requirements. However, it should specify M-mode access protection from lower privilege modes for platforms that do implement M-mode. O

On Thu, Oct 14, 2021 at 2:11 PM Aaron Durbin <adurbin@...> wrote: Out of curiosity, do you have a system you're designing that uses a custom alternative to PMP? Yes, we have an internal doc, and we in

Hi All, The meeting minutes for this meeting are uploaded to our usual location on platform wiki here https://github.com/riscv/riscv-platform-specs/wiki/2021.11.01:-Working-Group-Meeting Decisions tak

Hi All, The next platform HSC meeting is scheduled on Mon Nov 1st 2021 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki

Hi All, As per the platform HSC meeting on 10/25/2021 at 8AM PST, the following was agreed by a majority of participants on the call as well as past participants and multiple distro reviewers: The M-m

As per feedback, reduced basic UEFI requirements to 2.6.1 of the UEFI spec. Added reason to understand why additional protocols need to be supported on top of basic requirements. Signed-off-by: Sunil

Mark Himelstein (cto riscv) is inviting you to a scheduled Zoom meeting. Topic: Mark Himelstein (cto riscv)'s Personal Meeting Room Join Zoom Meeting https://zoom.us/j/4094940114 Meeting ID: 409 494 0

An issue is being raised in RVI over the overloaded naming of arch features, profile names, and platform names using "M". At an arch level, M mode is officially established. But then there are RVM* pr

As per feedback, reduced basic UEFI requirements to 2.6.1 of the UEFI spec. Added reason to understand why additional protocols need to be supported on top of basic requirements. Signed-off-by: Sunil