Anup, As you probably are aware now, the Mon @ 8am slot is taken by the Platforms group when the US DST switch occurs in March. What about polling to see if the Mon @ 7am would work? Greg

Hi All, Most of the communication and reviews for AIA specification/software will happen on this mailing list but it would be nice to sync-up once a month at least. Please provide your preferred time-

We extend SBI HSM extenstion by adding hart suspend function. This hart hart suspend function provide a standard interface for platform specific suspend (or low power) states and it can be used by sup

should an OS person weigh in on this? I asked previously about COW and was told a reserved bit could be used. ---------- Forwarded message --------- From: Greg Favor <gfavor@...> Date: Fri, Feb 26, 20

Understood. (I had assumed by default that the time, like with most TG's, wouldn't change with DST.) Btw, note that at 9am PT this meeting will sometimes conflict with the J extension group's meeting

Hi, The next platform meeting is scheduled on 8th march 7AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki Here are the slide

Up to now the SBI specification does not define how unsupported EIDs and FIDs shall be handled. Require returning error code SBI_ERR_NOT_SUPPORTED. Signed-off-by: Heinrich Schuchardt <xypron.glpk@...>

Hi All, As we spoke during the meeting today, below are the chapters that we need owners for. We are looking for volunteers to own and write each of these chapters. Please review and provide feedback

The HSM suspend function will bring new HSM states and more tables. This patch improves HSM documentation so that adding new HSM states is straight forward and we can cross-reference tables from HSM f

This series does few improvements to SBI HSM documentation and adds SBI HSM suspend call. Changes since v3: - Minor typo fixes in platform-coordinated and OS-initiated approaches - Made suspend_type p

The SBI specification uses a constant XLEN multiple times in the text without defining it. I assume XLEN is the bitness of the RISC-V implementation (32, 64, or 128). Furthermore reference is made to

The length of int, long, unsigned long is compiler specific. We do not wan= t to require the SBI and the operating system to use the same compiler. Instead the SBI standard shall define a binary inter

The following is an update to the platform spec in terms of adding the relevant chapters as discussed during the bi-monthly platform meetings. I have added the sub-sections here as well to serve as a

This series: 1) Further improves SRST documentation 2) Adds table captions and use cross-reference for citing tables Anup Patel (2): Improvements to SRST documentation Add table caption and use table

This patch does following improvements to the SBRST extension documentation: 1) The reset_type and reset_reason are 32bit parameters so fix sbi_system_reset() function prototype accordingly 2) Use cap

This patch adds caption to all tables and use cross-reference to refer tables in text. Also, we add SBI version column in all SBI function listing tables. Signed-off-by: Anup Patel <anup.patel@...> --

From: Anup Patel <anup.patel@...> This patch adds SBI performance monitoring unit (PMU) extension which allows S-mode (or VS-mode) software to configure hardware/software performance counters with hel

From: Guo Ren <guoren@...> Current riscv is still using baby spinlock implementation. It'll cause fairness and cache line bouncing problems. Many people are involved and pay the efforts to improve it:

From: Guo Ren <guoren@...> Remove unnecessary marco, they are no use or handled by generic files (atomic-fallback.h, asm-generic/cmpxchg*). Signed-off-by: Guo Ren <guoren@...> Link: https://lore.kerne

From: Guo Ren <guoren@...> To reduce assembly codes, let's merge duplicate codes into one (xchg_acquire, xchg_release, cmpxchg_release). Signed-off-by: Guo Ren <guoren@...> Link: https://lore.kernel.o