Hi All, The slides from today's AIA meeting are here: https://docs.google.com/presentation/d/1WHGm7ZpOkVlk_sAVYVU5UwBXt1cdH-8fM1s2vdpY6K4/edit?usp=sharing Both AIA and ACLINT specifications are now on

This is an initial patch for PCIe requirements for the server extension. The goal is to specify requirements for those PCIe elements which interact with the system such as PCIe config space, memory sp

Mention that an SBI extension shall not be partially implemented. Signed-off-by: Bin Meng <bmeng.cn@...> --- Changes in v2: - %s/a SBI/an SBI - reword the clarification riscv-sbi.adoc | 6 ++++++ 1 fil

Signed-off-by: Bin Meng <bmeng.cn@...> --- riscv-sbi.adoc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/riscv-sbi.adoc b/riscv-sbi.adoc index 11c30c3..8696f97 100644 --- a/riscv-sbi.adoc +++

From: Abner Chang <renba.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. On v6 commit, Remove the changes in Embedded-2022 section. On v5 commit, - Remove CLINT from platf

This patch adds SBI performance monitoring unit (PMU) extension which allows S-mode (or VS-mode) software to configure hardware (or firmware) performance counters with help of M-mode (or HS-mode) soft

%s/secion/section/ %s/managment/management/ %s/implemenation/implementation/ %s/requestd/requested/ %s/hierarchial/hierarchical/ %s/inititated/initiated/ %s/recieves/receives/ %s/rententive/retentive/

%s/a SBI/an SBI/ %s/A SBI/An SBI/ Signed-off-by: Bin Meng <bmeng.cn@...> --- riscv-sbi.adoc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/riscv-sbi.adoc b/riscv-sbi.ad

Hi All, The next platform HSC meeting is scheduled on Fri Jun 4th at 8AM PST. This is a new slot only for this week due to Monday being a holiday in the US for Memorial Day and Wed being the RISC-V to

Signed-off-by: Paul Donahue pdonahue@... --- riscv-platform-spec.adoc | 101 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/riscv-platform-spec.adoc b/riscv-plat

Thanks for writing this up, Anup. In https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc#24-synchronizing-multiple-mtimer-devices, the SW algorithm should include verifying the referen

One other issue with the "mtime" synchronization by SW approach is that this effectively places an upper limit on the achievable timer unit resolution. It'd be some equation based on the ordered acces

From: Abner Chang <abner.chang@...> Signed-off-by: Abner Chang <renba.chang@...> --- contributors.adoc | 1 + 1 file changed, 1 insertion(+) diff --git a/contributors.adoc b/contributors.adoc index 91c

From: Abner Chang <abner.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. On v6 commit, Remove the changes in Embedded-2022 section. On v5 commit, - Remove CLINT from platf

From: Abner Chang <renba.chang@...> Signed-off-by: Abner Chang <renba.chang@...> --- contributors.adoc | 1 + 1 file changed, 1 insertion(+) diff --git a/contributors.adoc b/contributors.adoc index 3d1

Updating changelog Signed-off-by: Paul Donahue pdonahue@... --- changelog.adoc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/changelog.adoc b/changelog.adoc index 7ec1b1f..cc69971 100644 --- a/c

Adding myself to list of contributors. Signed-off-by: Paul Donahue pdonahue@... --- contributors.adoc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/contributors.adoc b/contributo

From: Abner Chang <renba.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. On v5 commit, - Remove CLINT from platform spec - Require ACLINT on Linux2020 platform and have a

Hi All, The RISC-V ACLINT specification is now hosted on RISC-V GitHub page: https://github.com/riscv/riscv-aclint https://github.com/riscv/riscv-aclint/blob/master/riscv-aclint.adoc Please review thi

From: Abner Chang <renba.chang@...> Initial description of PLIC CLINT section of Linux-2022 platform. Is this what we want to see of CLINT/Machine mode timer in the platform spec? On v4 commit, - PLIC