Hello Sunil, Thanks for sending out these ECRs. After looking at these documents, we have a lot of comments/questions, but I think it might be productive to walk through the assumptions and approach f

Hi All, Based on feedback, below is the updated draft proposal of the SBI Debug Console Extension ... The motivations behind this proposal is as follows: 1) There is no new SBI extension replacing the

You have been invited to the following event. Ad-hoc ACPI ECR Review meeting When Mon Jun 27, 2022 9:30pm – 10:30pm India Standard Time - Kolkata Joining info Join with Google Meet meet.google.com/dao

Although the deadline has past, it was mentioned at the Software HC meeting last week that there are no candidates for the vice-chair position, so I would like to nominate myself. I have been involved

we have seen a number of SBI changes proposed (debug console, ap tee, ...). will there be one big rev ala priv 1.12, small fast tracks , something else? I also suggest that this either needs to be run

Hi All, Below is the draft proposal for SBI Debug Console Extension. Please review it and provide feedback. Thanks, Anup Debug Console Extension (EID #0x4442434E "DBCN") ==============================

That is because it is useful to have debug console output when porting a hypervisor or baremetal code to a new board. Of course, if a hypervisor is already available for the board, then it would be ju

Hi Anup, Here are my thoughts: * Guest memory access: I think this would be the first SBI extension to require access to guest memory. This needs to be considered carefully, but I think the higher ban

It's also helpful in early board bringup and early debugging as pointed out by Heiko as well. To address some of the concerns raised above, how about putting some restrictions on sbi_debug_console_set

Thanks, it will be nice to drop putchar. What is the motivation for `area_offset`? Will the supervisor use different offsets for different harts? What are the advantages and disadvantages of the offse

Hi All, My apologies for the long email up front. I hope people find this useful as well as a starting point for a broader discussion in how all these pieces fit together within RISC-V. There are impl

All, As per the policy governing chairs and vice chairs, we are holding a call for candidates for the positions of CHAIR and VICE-CHAIR for the OS-A SEE TG. To nominate yourself or another member of t

Hi All, I am pleased to inform that 45 days of public review period has ended for the RISC-V UEFI Protocol Spec. Feedbacks during review period are addressed. We will go through the remaining process

Hi All, I'm cross posting to tech-unixplatformspec@ and tech-os-a-see@ lists because there wasn't sufficient overlap in membership to get the proper visibility. I had proposed a charter that can be fo

Hi, I have some questions related to the Watchdog spec found here: https://github.com/riscv-non-isa/riscv-watchdog/blob/main/riscv-watchdog.adoc 1. The spec goes to great lengths to describe the watch

I haven't been following the H extension closely, and was not aware the HBI/HEE terms have suffered the same fate. This is one of those things that makes it hard to convince people to take RISC-V seri

Add requirement for preserving the PCIe ID routing as described in issue: https://github.com/riscv/riscv-platform-specs/issues/81 Signed-off-by: Mayuresh Chitale <mchitale@...> --- riscv-platform-spec

Currently the SBI specification defines how to hand device-trees from the SEE to the S-mode firmware. In the context of Trusted Firmware A a document has been developed describing what a more generic

Hi All, The next platform HSC meeting is scheduled on Mon Apr 4th 2022 at 8AM PST. Here are the details: Agenda and minutes kept on the github wiki: https://github.com/riscv/riscv-platform-specs/wiki

UEFI uses to talk of configuration tables not of firmware tables. Add missing 'the', 'and'. Enhance readability of sentence concerning ExitBootServices(). Signed-off-by: Heinrich Schuchardt <heinrich.