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Request for the new CSRs


Adam Zabrocki <azabrocki@...>
 

Dear Unprivileged Standing Committee,

The J-Ext and TEE groups are working on a Pointer Masking (PM) extension. This feature provides a possibility of implementing memory address tagging, memory sandboxes, pointer compression and more by ignoring various bits (defined by a mask) of the effective address (virtual or physical) on RV128, RV64 and RV32. More details can be found on the J-Ext github repo:

https://github.com/riscv/riscv-j-extension/blob/master/pointer-masking-proposal.adoc

The proposal requires adding three new CSRs for each privilege mode. We propose to add:

  • a new PM configuration CSR register called MMTE (Memory Tagging Extension)
  • a new PM pointer masking CSR register for each privilege mode called MPMMASK (Pointer Masking Mask)
  • a new PM pointer base CSR register for each privilege mode called MPMBASE (Pointer Masking Base)

Restricted views of the mmte register appear as the smte, vsmte and umte registers in HS/S-mode, VS-mode and (V)U-mode, respectively.

Each privilege mode has its own pointer masking CSR register. It appears as the mpmmask, spmmask, vspmmask and upmmask registers in M-mode, HS/S-mode, VS-mode and (V)U-mode, respectively.

Each privilege mode has its own pointer base CSR register. It appears as the mpmbase, spmbase, vspmbase and upmbase registers in M-mode, HS/S-mode, VS-mode and (V)U-mode ISAs, respectively.

We are working towards ratification of this proposal and are asking for approval to add these CSRs. Preferably, we would like these CSRs to have consecutive CSR numbers, with an additional 3 numbers kept free in case of future extensions (for a total of 12 CSR number reservations). Can you kindly review the proposal and assign new CSRs?

Thanks!

Adam