I've started a new thread. TLDR; I see the argument of Two keys as circular and unnecessarily restrictive. This was to allow a common means of implementing "I" base without requiring actual misaligned

>I'm not sure how we get tools/compilers to avoid DIV/REM instructions, which is one of the final missing pieces According to this: https://gcc.gnu.org/onlinedocs/gcc/Option-Summary.html RISCV GCC alr

I think I volunteered to write this up for some meeting or another, so here it is, long overdue I think: (slightly updated with spelling/grammar corrections & a bit more explanation) Chapter x+1 “Zmmu

Hi everyone, I think there’s a problem with the Zfinx + Zfh configuration. Currently, as agreed on email, the configs are: Z[FDQ]inx And to include Zfh Z[FDQ]inx_Zfh But I think this isn’t right as th

(I change TECH-TEE to TECH-UNPRIV on CC) Yes – very interesting. We can detect Zfinx by checking that Misa.F is read-only 0 Mstatus.FS is read-only 0 Accesses to FCSR don’t trap. And I agree there’s n

Hi everyone, This started as a thread on the Zfinx mailing list but I think unpriv is a better place for it. https://github.com/riscv/riscv-zfinx/issues/8 Basically Jessica is complaining that F and Z

A recap for Mark: We’ve had a complaint from an upstream LLVM developer about Zfinx, because it *changes* the F and D extension. And it has the same effect on V, which also uses F registers (e.f. vfmv

Hi Greg, For now, here is a summary of my understanding of a comparison of PAUSE.LR vs MONITOR/WAIT. This is primarily based on my understanding of MIPS PAUSE, with a superficial understanding of x86

Hi everyone, The question of 48-bit encodings came up in the code size meeting today. Mark Himelstein pointed out that if any such encodings are to be allowed in RVA22/RVM22 then the extension mechani

Hi Allen, Pls see my comment in green. From: Allen Baum <allen.baum@...> Date: Tuesday, January 5, 2021 at 11:27 PM To: "tech-unprivileged@..." <tech-unprivileged@...>, Greg Favor <gfavor@...> Cc: San

Hi Folks, We have defined a custom instruction equivalent to MIPS PAUSE which deschedules the instruction stream when an LL(==RISC-V LR) fails to acquire the lock. If a snoop is detected against the L

Dear Unprivileged Standing Committee, The J-Ext and TEE groups are working on a Pointer Masking (PM) extension. This feature provides a possibility of implementing memory address tagging, memory sandb

Hi everyone, Following discussions with Krste, he has decided to allow reuse of a subset of 16-bit encodings for code-size reduction instructions. This is a very important step for the code-size reduc

Hi everyone, From the instruction encoding policy: https://docs.google.com/document/d/1uC6QAyFmglGbO9kRR-X8LQWga6B3yBJR7-iw6ZXnfG8/edit# “The basic meaning of an instruction encoding shall not be depe

This is just a quick FYI. (Sorry if this is a bit spam'y; there isn't a clear TG to target with this email. And I don't expect that this is something that plays into any near-term RISC-V standardizati

At the open source for him I just got asked by a gentleman name Shavon Pantar about Xpulp which is being done by ETH. He would like to see about making this a standard extension. I believe it falls un

Hi all, Recently the TSC established a lightweight "fast track" architecture extension process that small, straightforward, relatively uncontentious arch extension proposals can utilize (instead of ha

I broke one of my cardinal rules of email and sent out a call-to-action without clearly stating this in the subject. I am resending the key portion of my email under a more descriptive subject line. M

Hi unpriv. Standing Committee The TEE group is working on a PMP extension proposal to enhance PMP security, see https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit?usp

Thanks, Ken. From: <tech-tee@...> on behalf of Ken Dockser <kdockser@...> Date: Wednesday, October 7, 2020 at 11:01 PM To: "tech-unprivileged@..." <tech-unprivileged@...>, Joe Xie <joxie@...> Cc: Andr