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[RISC-V] [tech-config] Discovery mechanism for Zfinx 13 messages
(I change TECH-TEE to TECH-UNPRIV on CC) Yes – very interesting. We can detect Zfinx by checking that Misa.F is read-only 0 Mstatus.FS is read-only 0 Accesses to FCSR don’t trap. And I agree there’s n
(I change TECH-TEE to TECH-UNPRIV on CC) Yes – very interesting. We can detect Zfinx by checking that Misa.F is read-only 0 Mstatus.FS is read-only 0 Accesses to FCSR don’t trap. And I agree there’s n
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By Tariq Kurd
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Zfinx and mutated extensions 8 messages
Hi everyone, This started as a thread on the Zfinx mailing list but I think unpriv is a better place for it. https://github.com/riscv/riscv-zfinx/issues/8 Basically Jessica is complaining that F and Z
Hi everyone, This started as a thread on the Zfinx mailing list but I think unpriv is a better place for it. https://github.com/riscv/riscv-zfinx/issues/8 Basically Jessica is complaining that F and Z
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By Tariq Kurd
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FW: [RISC-V] [tech-unprivileged] Zfinx and mutated extensions
A recap for Mark: We’ve had a complaint from an upstream LLVM developer about Zfinx, because it *changes* the F and D extension. And it has the same effect on V, which also uses F registers (e.f. vfmv
A recap for Mark: We’ve had a complaint from an upstream LLVM developer about Zfinx, because it *changes* the F and D extension. And it has the same effect on V, which also uses F registers (e.f. vfmv
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By Tariq Kurd
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[EXTERNAL]Re: [RISC-V] [tech-unprivileged] PAUSE for LR/SC 24 messages
Hi Greg, For now, here is a summary of my understanding of a comparison of PAUSE.LR vs MONITOR/WAIT. This is primarily based on my understanding of MIPS PAUSE, with a superficial understanding of x86
Hi Greg, For now, here is a summary of my understanding of a comparison of PAUSE.LR vs MONITOR/WAIT. This is primarily based on my understanding of MIPS PAUSE, with a superficial understanding of x86
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By Sanjay Patel
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48-bit encodings 6 messages
Hi everyone, The question of 48-bit encodings came up in the code size meeting today. Mark Himelstein pointed out that if any such encodings are to be allowed in RVA22/RVM22 then the extension mechani
Hi everyone, The question of 48-bit encodings came up in the code size meeting today. Mark Himelstein pointed out that if any such encodings are to be allowed in RVA22/RVM22 then the extension mechani
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By Tariq Kurd
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[EXTERNAL]Re: [RISC-V] [tech-unprivileged] PAUSE for LR/SC
Hi Allen, Pls see my comment in green. From: Allen Baum <allen.baum@...> Date: Tuesday, January 5, 2021 at 11:27 PM To: "tech-unprivileged@..." <tech-unprivileged@...>, Greg Favor <gfavor@...> Cc: San
Hi Allen, Pls see my comment in green. From: Allen Baum <allen.baum@...> Date: Tuesday, January 5, 2021 at 11:27 PM To: "tech-unprivileged@..." <tech-unprivileged@...>, Greg Favor <gfavor@...> Cc: San
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By Sanjay Patel
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PAUSE for LR/SC 3 messages
Hi Folks, We have defined a custom instruction equivalent to MIPS PAUSE which deschedules the instruction stream when an LL(==RISC-V LR) fails to acquire the lock. If a snoop is detected against the L
Hi Folks, We have defined a custom instruction equivalent to MIPS PAUSE which deschedules the instruction stream when an LL(==RISC-V LR) fails to acquire the lock. If a snoop is detected against the L
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By Sanjay Patel
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Request for the new CSRs
Dear Unprivileged Standing Committee, The J-Ext and TEE groups are working on a Pointer Masking (PM) extension. This feature provides a possibility of implementing memory address tagging, memory sandb
Dear Unprivileged Standing Committee, The J-Ext and TEE groups are working on a Pointer Masking (PM) extension. This feature provides a possibility of implementing memory address tagging, memory sandb
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By
Adam Zabrocki
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Re-use of 16-bit encodings between standard extensions 11 messages
Hi everyone, Following discussions with Krste, he has decided to allow reuse of a subset of 16-bit encodings for code-size reduction instructions. This is a very important step for the code-size reduc
Hi everyone, Following discussions with Krste, he has decided to allow reuse of a subset of 16-bit encodings for code-size reduction instructions. This is a very important step for the code-size reduc
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By Tariq Kurd
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Instruction encoding allocation policy and Zfinx 5 messages
Hi everyone, From the instruction encoding policy: https://docs.google.com/document/d/1uC6QAyFmglGbO9kRR-X8LQWga6B3yBJR7-iw6ZXnfG8/edit# “The basic meaning of an instruction encoding shall not be depe
Hi everyone, From the instruction encoding policy: https://docs.google.com/document/d/1uC6QAyFmglGbO9kRR-X8LQWga6B3yBJR7-iw6ZXnfG8/edit# “The basic meaning of an instruction encoding shall not be depe
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By Tariq Kurd
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ARM's new capability-based security ISA (building on top of ARMv8)
This is just a quick FYI. (Sorry if this is a bit spam'y; there isn't a clear TG to target with this email. And I don't expect that this is something that plays into any near-term RISC-V standardizati
This is just a quick FYI. (Sorry if this is a bit spam'y; there isn't a clear TG to target with this email. And I don't expect that this is something that plays into any near-term RISC-V standardizati
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By Greg Favor
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xpulp 5 messages
At the open source for him I just got asked by a gentleman name Shavon Pantar about Xpulp which is being done by ETH. He would like to see about making this a standard extension. I believe it falls un
At the open source for him I just got asked by a gentleman name Shavon Pantar about Xpulp which is being done by ETH. He would like to see about making this a standard extension. I believe it falls un
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By mark
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"PAUSE hint instruction" extension 4 messages
Hi all, Recently the TSC established a lightweight "fast track" architecture extension process that small, straightforward, relatively uncontentious arch extension proposals can utilize (instead of ha
Hi all, Recently the TSC established a lightweight "fast track" architecture extension process that small, straightforward, relatively uncontentious arch extension proposals can utilize (instead of ha
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By Greg Favor
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Instruction Encoding and CSR Allocation Process - call to action
I broke one of my cardinal rules of email and sent out a call-to-action without clearly stating this in the subject. I am resending the key portion of my email under a more descriptive subject line. M
I broke one of my cardinal rules of email and sent out a call-to-action without clearly stating this in the subject. I am resending the key portion of my email under a more descriptive subject line. M
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By Ken Dockser
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Request a new CSR address for pmp ext. 4 messages
Hi unpriv. Standing Committee The TEE group is working on a PMP extension proposal to enhance PMP security, see https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit?usp
Hi unpriv. Standing Committee The TEE group is working on a PMP extension proposal to enhance PMP security, see https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit?usp
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By Joe Xie
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[RISC-V] [tech-tee] Request a new CSR address for pmp ext.
Thanks, Ken. From: <tech-tee@...> on behalf of Ken Dockser <kdockser@...> Date: Wednesday, October 7, 2020 at 11:01 PM To: "tech-unprivileged@..." <tech-unprivileged@...>, Joe Xie <joxie@...> Cc: Andr
Thanks, Ken. From: <tech-tee@...> on behalf of Ken Dockser <kdockser@...> Date: Wednesday, October 7, 2020 at 11:01 PM To: "tech-unprivileged@..." <tech-unprivileged@...>, Joe Xie <joxie@...> Cc: Andr
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By Joe Xie
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FP instructions that depend on rounding mode 2 messages
The F extension says: "The behavior of floating-point instructions that depend on rounding mode when executed with a reserved rounding mode is reserved, including both static reserved rounding modes (
The F extension says: "The behavior of floating-point instructions that depend on rounding mode when executed with a reserved rounding mode is reserved, including both static reserved rounding modes (
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By Paul Donahue
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[RISC-V] [tech-privileged] P extension instruction opcode encoding allocation 2 messages
Krste has said (correct me if I am wrong) that the unpriv SC owns the opcode space. I know there is a lot of overlap in the SC members but I suggest we get that SC officially in the loop. I have CC'ed
Krste has said (correct me if I am wrong) that the unpriv SC owns the opcode space. I know there is a lot of overlap in the SC members but I suggest we get that SC officially in the loop. I have CC'ed
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By mark
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