Re: Thoughts on Git update (8a9fbce) Added fractional LMUL, including modifying vector data register and vector mask register layouts for SLEN<VLEN implementations.
On Sat, 25 Apr 2020 23:02:08 -0400, DSHORNER <ds2horner@...> said: | On 2020-04-25 8:46 p.m., krste@... wrote: || On Sat, 25 Apr 2020 18:23:07 -0400, "David Horner" <ds2horner@...> said: [...] | The wasteful of space still applies (As does the dynamic VLEN to have | useful re-nameable tails)
The space in a fractional LMUL register can be used in software. E.g., by loading an SEW=8 vector with LMUL=1, then using LMUL=1/4 to combine first quarter with SEW=32,LMUL=1 vectors in other registers. Once the first quarter of the source SEW=8 vector register is processed, a slidedown by vlenb/4 can be used to align the next SEW=8,LMUL=1/4 vector of operands (though currently have to reset SEW/LMUL around the slidedown to avoid zeros appearing).
Yes. The register is not tainted by having been used as fractional. But what I was meaning was that there is no active use of that space during fractional mode.
That temporary switch to slidedown can be assisted by the transient version of #423, additional instructions to set vtype fields.
