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  2. Vector Task Group minutes 2020/5/15 - V0.8 design with SLEN=8

Re: Vector Task Group minutes 2020/5/15 - V0.8 design with SLEN=8

Bruce Hoult
 

On Fri, May 29, 2020 at 10:27 AM David Horner <ds2horner@...> wrote:
I have some suggestions for the reasons for moving from v0.8 vertical striping to v0.9 horizontal SLEN (interleave)

Under  v0.8
A)   when vl < VLEN/SEW*LMUL the top elements are not filled.
            This can lead to under utilization of the top lanes.
            Even though vl is 1/2 or less of the max,  all registers in the group are referenced, and hence slower and more power use in the general case.

I seem to recall that at some point LMUL was only a suggestion and that if the requested vl was short (e.g. the last strip-mining loop on a long application vector) the vsetvl[i] instruction was free to reduce the requested LMUL.

Maybe that was back in 0.7, but I think it should still work with type punning as long as vl*EW is always the same (which it has to be anyway).
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