- On Vector Register Layout
Re: On Vector Register Layout
On Fri, Jun 12, 2020, 07:05 Krste Asanovic, <krste@...
TL;DR: I'm leaning towards mandating SLEN=VLEN layout, at least for
application processor profiles.
I agree that this should be default or base configuration.
The interesting cases are mixed-width operations, which are prevalent
in low-precision multiply-accumulate kernels that dominate many
existing and emerging compute areas, but there are plenty of other
kernels that operate on mixed-width data items. Classic SIMD ISAs
handle mixed-width operations in one of five ways (would be glad to
add other known options to this list):
I believe the extended fractional layout is a 6th approach. Issue 465. Does it qualify as a known option?
As with option 2 load and stores format the data for widening operations. However the data remains in single width and the widening instructions.
This approach ensures software is aware as explicit layout formatting is required in advance of the widening instructions.
Join firstname.lastname@example.org to automatically receive all group messages.