There are 19 open issues that aren't yet labeled.

Does it make sense that those who will be on the call review them with an idea to categorize as for or after V1.0?
That should also determine those that need further investigation and will also familiarize us with the issues.

Thanks.

Relax constraint on vl exceeding register group effective VLEN.

https://github.com/riscv/riscv-v-spec/issues/#527 opened 3 hours ago by David-Horner

relax LMUL constraint on load/store (vl*eew determines LMUL value)

https://github.com/riscv/riscv-v-spec/issues/#523 opened yesterday by David-Horner

overlap of destination register with sources on VRED operations

https://github.com/riscv/riscv-v-spec/issues/#522 opened 2 days ago by respasa

vcompress --> vdecompress

https://github.com/riscv/riscv-v-spec/issues/#521 opened 3 days ago by HKLee2040

vrgather SEW=8b only works up to 256 elements

https://github.com/riscv/riscv-v-spec/issues/#520 opened 3 days ago by respasa

Reserve ELEN of 1024, 512 and 256 and instruction encodings for them (was: e1024 encoding ( in load/store (mew-width) for all forms of element sized load/stores.))

https://github.com/riscv/riscv-v-spec/issues/#519 opened 3 days ago by David-Horner

2

Vector Load/Store Whole Register Instruction formats

https://github.com/riscv/riscv-v-spec/issues/#517 opened 4 days ago by JamesKenneyImperas

1

Possible conflict between vector register grouping (3.3.2) and ELEN > VLEN?

https://github.com/riscv/riscv-v-spec/issues/#515 opened 6 days ago by JamesKenneyImperas

3

Relaxing constraints moving from drafts to specifications

https://github.com/riscv/riscv-v-spec/issues/#513 opened 8 days ago by David-Horner

[question] how to build the vtype for vsetvl instruction?

https://github.com/riscv/riscv-v-spec/issues/#511 opened 9 days ago by JerryShih

5

{le} and {ge} do not render in anything besides body-text

https://github.com/riscv/riscv-v-spec/issues/#506 opened 10 days ago by BrianGraysonSiV

2

Matrix Multiplication Example

https://github.com/riscv/riscv-v-spec/issues/#495 opened 28 days ago by JamesKenneyImperas

5

Tips&tricks for decoding of instructions

https://github.com/riscv/riscv-v-spec/issues/#494 opened on Jun 9 by Marc43

1

unbind vstart from element index

https://github.com/riscv/riscv-v-spec/issues/#493 opened on Jun 5 by jnk0le

2

why riscv-v-spec-0.9.html just list vle32 and vle64 instructions

https://github.com/riscv/riscv-v-spec/issues/#489 opened on May 28 by luxufan

2

Note on MLEN=1 (reduced functionality compared to 0.8)

https://github.com/riscv/riscv-v-spec/issues/#481 opened on May 18 by JamesKenneyImperas

1

ISA support to Managing implementation dependent characteristics

https://github.com/riscv/riscv-v-spec/issues/#476 opened on May 16 by David-Horner

Clarify version features

https://github.com/riscv/riscv-v-spec/issues/#431 by JamesKenneyImperas was closed on Apr 30

4

Encode ELEN to sub-extension, Zve64, Zve128, Zve256...

https://github.com/riscv/riscv-v-spec/issues/#360 opened on Jan 9 by kito-cheng

On 2020-07-03 5:08 p.m., Krste Asanovic wrote:

Date: 2020/7/03
Task Group: Vector Extension
Chair: Krste Asanovic
Co-Chair: Roger Espasa
Number of Attendees: ~6
Current issues on github: https://github.com/riscv/riscv-v-spec

This call was sparsely attended due to US Independence day holiday.