On Wed, Jul 22, 2020 at 11:42 PM <krste@...> wrote:

>>>>> On Wed, 22 Jul 2020 23:37:02 -0700, Andrew Waterman <andrew@...> said:

| On Wed, Jul 22, 2020 at 11:19 PM David Horner <ds2horner@...> wrote:

|     #3) If vill is set should vl remain unchanged? (I vote for yes).

| Other vsetvl[i] instructions that set vill=1 also set vl=0.  Deviating from that course would be needlessly painful and not especially beneficial.

It does add a non-orthogonality, but it is certainly beneficial in
renamed machines to know that vl is never changed by the instruction.

Disagreed. It’s fine to treat vsetvl instructions that set vill as pipeline flushes. Uarch can therefore assume vl isn’t changed.

In my response to your prior post I stated that #1 and #3 are needed to guarantee vl invariance in speculative cases.
I agree with you that such a guarantee is not needed, as assumption is adequate to speculatively proceed.
So, ignore my "iff"s and "buts" about #3 for aggressive ooo.


I will think through diagnostic and recovery value.
And if there is any potential benefit to other Uarch than aggressive ooo.

Thanks.

Krste