I'm sending out to the correct mailing list a copy of the
revised issue #393.
This was requested at the last TG meeting.
I believe it is consistent with casual discussions of fractional LMUL and it is intended to formalize a design.To follow is the consideration of alternate register overlap to improve usability.
The issue #393 update adds to the Glossary and notes that mask registers and operations are unchanged from the plan of record.
Prior to LMUL, an elaborate mapping of registers numbers to various width element under different configuration settings that allowed for polymorphic operations was proposed.
LMUL was introduced in a pre-v0.5 Nov 2018 in conjunction with
widening operations and SEW widths.
This issue will look at simplest implementations of fraction LMUL.
base-arch registers* – the 32 registers addressable when LMUL=1
The simplest extensions to the base retain the
The simplest extension of LMUL to “fractional” is that
the observe affects continue predictably.
For LMUL >=1, VLMAX = LMUL * VLEN/SEW
This table exhaustively represents this simplest extension effect when SEW is unchanged throughout:
Fractional registers then have diminished capacity, 1/2 to 1/8th of a base-arch register.
The simplest mapping of fractional LMUL registers is
one to one (and only one) of the base-arch registers.
The simplest overlay (analogous to the register group
overlay of consecutive base-arch registers) is with zero
I call this iteration zero of the simplest fractional LMUL designs.
Note: Mask behaviour does not change. Mask operations read and write to a base-arch register. Base-arch register zero remains the default mask register. With this "iteration zero" design, as with LMUL>=1, fractional LMUL “register zero”s are substantially limited in their use.
There are some undesirable characteristic of this design.