Guy pointed out to me that, since several V ISA-design issues have been punted to an eventual 64-bit instruction encoding, we should consider recording them somewhere.  I've set up the github wiki for the purpose of recording design rationale that doesn't belong in the spec proper, and have seeded it with a very short list of hypothetical 64b features.  Feel free to edit directly if you have write permissions. https://github.com/riscv/riscv-v-spec/wiki