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- Vector Memory Ordering
Re: Vector Memory Ordering
Guy Lemieux <guy.lemieux@...>
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In less concerned with making the FIFO example work, and more concerned with ensuring programs are fully portable across all implementations.
Programmers don’t tend to read ISA specs and details. They try it, and infer behaviour from the implementations they have available to them. Hence, I believe there is a risk that many programmers will assume ordered stores in particular, but also ordered loads.
The ISAa cost of providing 2 modes, ordered and unordered, is either 1 bit in the ISA encoding or a mode bit along the lines of setvl. The implementation cost is nearly zero. The benefit is fully portable programs without surprises.
On Fri, Sep 4, 2020 at 12:54 PM Bill Huffman <huffman@...
Guy Lemieux commented:
I think 90%+ of implementations will choose to do ordered loads and stores even though unordered is permitted.
This means programmers will expect them to be ordered, and such software will not work properly on the remaining implementations. This compatibility problem is a concern.
I think the best way to combat this is to have 2 sets of instructions: ordered and unordered. The unordered implementation can simply do the ordered thing in simple implementations.
Ordered stores to a FIFO is a paradigm I was hoping to use for inter-processor communication.
I think compiler considerations are also important, but I don’t know the implications here.
Maybe what's below could be improved by saying that if the base address (in src1) was non-idempotent or an "ordered channel," the entire instruction would run in order. If not, it would not. We could allow stride of zero
but not other overlapping strides for stores. Having a later access come into a non-idempotent or ordered region would raise an exception. That would provide for loads from and stores to a FIFO to work. But it wouldn't provide for an instruction to "fall
into" such a memory segment part way through.
On 9/4/20 10:18 AM, Bill Huffman wrote:
I think from this morning, we are considering:
- Ordered scatters are done truly in order
- Strided stores that overlap (including segmented ones) will trap as illegal
- All other vector loads and stores do their memory accesses in arbitrary order.
- A vector load that accesses the same location multiple times is free to use the same loaded value for any subset of results
- All loads with vector sources must use a different register for the destination than any source (including mask).
- Maybe a vector load may access the memory location corresponding to a given element multiple times (for exception handling)??
A few of the consequences of this are:
- A gather with repeated elements can access the higher numbered elements first and lower ones later
- A vector memory access where multiple elements match watchpoint criteria can trap on any of the multiple elements, regardless of watchpoint requirements on order
- A stride-0 load accessing an "incrementing" location can see a result with larger values at lower element numbers than smaller values
- When vector loads or stores access an "ordered channel" the elements will still be accessed in arbitrary order
- Strided loads, gathers, and unordered scatters to non-idempotent regions will not behave as might be expected.
- A stride-0 store to a FIFO will trap
- A stride-0 load to a FIFO will pop an arbitrary number of entries from the FIFO (from 1 to more than vl) and elements are distributed in an arbitrary way in the result.
- A non-idempotent memory location accessed by a vector load may be accessed multiple times.
We need to be sure software is OK with these characteristics as "ordered channels" and non-idempotent regions can't be known at compile time. Even strides can't always be known at compile time. Will this plan reduce the amount
of auto-vectorization that can be done?
Exception reporting still has issues:
- Unless stores can be done multiple times, there is a need to save some representation of what stores have and have not been done.
- For loads and stores, watchpoints can happen more than once without some representation of what elements are complete.
- There may need to be a way to report a watchpoint on one element but restart on an earlier element
- If loads have to do this exception reporting as well, do we forbid loads to happen more than once for each element? Does that help anything if we do?
I'd like to see us relax the ordering of gathers and unordered scatters with younger instructions in some way. If we don't, younger scalar memory accesses will stall for some time as comparisons are much more difficult than
for unit stride or even strided accesses.
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