an interesting paper

Krste Asanovic

They mention RISC-V vectors in the intro, but on a quick scan, the
results are very ARM-specific, with no real implication for RISC-V
vectors. They're pointing out a problem with ARM SVE where all
elements are executed regardless of vector length due to SVE using
predication to implement vector length.


On Mon, 14 Sep 2020 08:46:05 -0500, "swallach" <steven.wallach@...> said:
| i was made aware of this paper. risc-v vectors are mentioned.
| one of the key conclusions are (from the abstract)

| Our experiments show that VLA code reaches about 90% of the performance of
| vector length specific code, i.e. a 10% overhead is inferred due to global
| predication of instructions. Furthermore, we show that code performance is not
| increasing proportionally with increasing vector lengths due to the higher
| memory demands.

| my experience is just the opposite. (based on memory system design)

| i am curious to hear other opinions

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