Re: Mask Register Value Mapping
On Wed, Sep 23, 2020, 15:10 CDS, <cohen.steed@...> wrote:
Word of caution: there may be a utility/readability concern if the ".LSB" text is removed, only.
This would create a phrase
vs2[i] + vs1[i] + v0[i]
which can easily be misleading to the reader - while 'i' has the same value for all three terms, the first two indicate a SEW bit field, whereas the final term indicates a single bit.
Suggestions: include a reminder that v0[i] entries are a single bit under the opening comment in the code block ("Produce sum with carry."); Set a reminder at the bottom of the description section before starting the code text, or indicate a comment on the code line "#Vector-vector-bit".
Or my preference a similar annotation that explicitly identifies it as a mast bit:
vs2[i] + vs1[i] + v0[i].m