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Re: 64-bit instruction encoding wish list

Claire Wolf <claire@...>
 

My current "long instruction encoding" proposal has an example encoding for 64-bit V extension instructions:

this contains everything currently in that wiki except
- Indexed memory accesses that implicitly scale the index by SEW/8
- Indexed memory accesses that decouple index width from data width

where can I find more information on this?

On Wed, 11 Mar 2020 at 04:08, Richard Newell <richard.newell@...> wrote:

Hi all,

 

I am not sure if these require 64-bit encoding, but I am interested in extended data types, especially signed-integer-complex, single-precision floating-point complex, and unums.

 

Rich

 

 

G. Richard Newell

Assoc. Technical Fellow, FPGA Business Unit, Microchip Technology

(408) 643-6146 (office), (408) 882-4785 (mobile), +1 (925) 478-7258 (Skype)

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From: tech-vector-ext@... [mailto:tech-vector-ext@...] On Behalf Of Andrew Waterman
Sent: Tuesday, March 10, 2020 5:33 PM
To: tech-vector-ext@...
Subject: [RISC-V] [tech-vector-ext] 64-bit instruction encoding wish list

 

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Guy pointed out to me that, since several V ISA-design issues have been punted to an eventual 64-bit instruction encoding, we should consider recording them somewhere.  I've set up the github wiki for the purpose of recording design rationale that doesn't belong in the spec proper, and have seeded it with a very short list of hypothetical 64b features.  Feel free to edit directly if you have write permissions. https://github.com/riscv/riscv-v-spec/wiki

 
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