On 2020-10-15 7:30 p.m., Andrew Waterman wrote:
My take is that requiring that element 0 either complete or trap is already a solid mechanism for guaranteeing forward progress, and cleanly matches the while-loop vectorization model.I agree, however, it still does not answer the ISA visible behavioural question: "Is the trap allowed to set vl=0 on return?"
Can this be compliant behaviour for certain platforms?
If so, then it would be equivalent to hardware doing the same thing, and thus the actual Vector hardware instruction should also be allowed this behaviour for the given platform.
This is a corollary of instruction emulation by trapping on unimplemented op codes.