Re: [RISC-V] [tech-cmo] Fault-on-first should be allowed to return randomly on non-faults (also, running SIMT code on vector ISA)
| First I am very happy that "arbitrary decisions by theOn Fri, 16 Oct 2020 07:48:00 -0400, "David Horner" <ds2horner@...> said:
| micro-architecture" allow reduction of vl to any [non-zero] value.
| Even if such appear "random".
| A check for vl=0 on platforms that allow it is eminently doable, low
| overhead for many use cases AND guarantees forward progress under
| SOFTWARE control.
If we allowed implementation to return vl=0, how does software
guarantee forward progress?
| I see it as no different [in fundamental principle] than other cases
| such as RVI integer divide by zero behaviour that does not trap but can
| be readily checked for.
| Also RVI integer overflow that if you want to check for it is at most a
| few instructions including the branch.
I don't see how these examples relate to returning vl=0 on some
microarchitectural event. The examples here have results that depend
only on architectural values, so can be deterministically handled.
vl=0 is more related to load-reserved/store-conditional failure, where
we need to add implementation constraints to guarantee forward