Re: Vector Task Group minutes 2020/12/04

David Horner

On Thu, Dec 10, 2020, 04:44 Bill Huffman, <huffman@...> wrote:
On the issue of what bits to load for vle1.v, we need to decide whether
these are byte loads of length ceil(vl/8) or whether they are bit loads
of length vl.  Bit loads _can_ have the additional bits as tail-agnostic
but must not have them as tail-undisturbed. 
I concur.
Software can effect tail-undisturbed by
A pre conditioning the load,
B loading into temp register then use bitwise logic into target,
C save last byte of target , lde1, read last byte, write the last byte of the merged two saved
In most cases this 'need' could be avoided by other means.
It would be nice if these
were bit loads, but it will be a little more complex for implementation
and I expect we may run into other issues down the line.  I think I lean
toward byte loads.

We have a similar issue for vse1.v as the remaining bits in the memory
byte _must_ be stored with something.  Here it seems simpler and perhaps
more logical to say this is a byte store with length ceil(vl/8) - which
helps re-enforce the choice of byte load for vle1.v.


On 12/4/20 7:01 PM, Krste Asanovic wrote:


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