Re: Vector Task Group minutes 2020/12/04


Bill Huffman
 

I don’t think a separate mask register will do at all. It would take a mask register file with at least 8 and maybe 16 registers. Lots of compare results need to be kept and operations need to be done on mask registers. I don't think we should have a separate mask register file.

Bill

-----Original Message-----
From: tech-vector-ext@lists.riscv.org <tech-vector-ext@lists.riscv.org> On Behalf Of swallach
Sent: Wednesday, December 16, 2020 12:26 PM
To: Alex Solomatnikov <sols@sifive.com>
Cc: Krste Asanovic <krste@berkeley.edu>; tech-vector-ext@lists.riscv.org
Subject: Re: [RISC-V] [tech-vector-ext] Vector Task Group minutes 2020/12/04

EXTERNAL MAIL


i totally agree. if this is done, then instructions like: count bits, etc can directly apply to the mask register.

also, from a hardware implementation, the VM register can be implemented with LATÇHES. this facilitates a better implementation (imho) for operations under mask

and yes load and store VM are required

——


If separate loads and stores are introduced for mask, then separate vmask register can be introduced to avoid dual use of v0 (as a regular vector register and as a mask register) and its complications.

Alex
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