1. tech-vector-ext@lists.riscv.org

Re: Vector Task Group minutes 2020/12/04

Alex Solomatnikov
 

One option is to allow mask generating instructions (compares) to write either to regular vector regs or to vmask and to provide move instructions between vector regs and vmask.

But mask consuming instructions can use only vmask as a mask. Mask load and store are also only for vmask.

This is no worse than current design.

Alex


On Wed, Dec 16, 2020 at 12:29 PM Bill Huffman <huffman@...> wrote:
I don’t think a separate mask register will do at all.  It would take a mask register file with at least 8 and maybe 16 registers.  Lots of compare results need to be kept and operations need to be done on mask registers.  I don't think we should have a separate mask register file.

      Bill

-----Original Message-----
From: tech-vector-ext@... <tech-vector-ext@...> On Behalf Of swallach
Sent: Wednesday, December 16, 2020 12:26 PM
To: Alex Solomatnikov <sols@...>
Cc: Krste Asanovic <krste@...>; tech-vector-ext@...
Subject: Re: [RISC-V] [tech-vector-ext] Vector Task Group minutes 2020/12/04

EXTERNAL MAIL


i  totally agree.  if this is done,  then instructions like:  count bits,  etc can directly apply to the mask register.

also,  from a hardware implementation,   the VM register can be implemented with LATÇHES.  this facilitates a better implementation (imho) for operations under mask

and yes load and store VM are required

——


If separate loads and stores are introduced for mask, then separate vmask register can be introduced to avoid dual use of v0 (as a regular vector register and as a mask register) and its complications.

Alex
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