Re: Minutes of 2020/3/20 vector TG meeting


Bill Huffman
 

On 3/23/20 12:37 PM, Krste Asanovic wrote:
EXTERNAL MAIL



Date: 2020/3/20
Task Group: Vector Extension
Chair: Krste Asanovic
Number of Attendees: ~20
Current issues on github: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_riscv_riscv-2Dv-2Dspec&d=DwIBAg&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-_haXqY&r=AYJ4kbebphYpRw2lYDUDCk5w5Qa3-DR3bQnFjLVmM80&m=3-SR1O6HM8Iu6jjTQmNtVVm49J8CuL1gmyiHKoiiA6Q&s=zZlo9CtETrWKKf8ZSBOIloLoVQ0w6upesOs7M7WK44k&e=
...

#393 Fractional LMUL additional registers

Proposal to add fractional LMUL to support a greater number of usable
architecture registers in presence of mixed-width operands.

There was discussion about the new proposal on mapping fractional LMUL
elements when systems have SLEN<VLEN, as it appeared to break SLEN
wiring optimization. A scheme that appears to address the datapath
wiring concern spreads out fractional LMUL elements along the register
was discussed in meeting

VLEN=128b, SLEN=64b
F E D C B A 9 8 7 6 5 4 3 2 1 0 Byte number

X X X X X X X X X X X X 0 0 0 0 LMUL=1/4, SEW=32b
X X X X X X X X 0 0 0 0 0 0 0 0 LMUL=1/2, SEW=64b

X X X X 1 1 1 1 X X X X 0 0 0 0 LMUL=1/2, SEW=32b
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 LMUL=1, SEW=64b

Discussion to continue on mailing list.
I assume that:

ELEN=64b here. It can't be smaller because SEW=64b is listed. It can't
be larger because SLEN=64b

LMUL=1/8, SEW=32b is illegal
LMUL=1/4, SEW=64b is illegal

LMUL=1/8, SEW=64b is illegal

The compiler knows these are illegal because it knows ELEN.

Bill





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