Are there any plans for a cut-down configuration of the vector extension suitable for embedded cores? It seems that the 32x128-bit register file is suitable for application class cores but it very large for embedded cores, especially if
the F registers also need to be implemented (which I think is the case, unless a Zfinx version is specified).
ARM MVE only has 8x128-bit registers for FP and Vector, so it much more suitable for embedded applications.
What’s the approach here? Should embedded applications implement the P-extension instead?
I RISC-V Cores, Bristol
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