Re: Smaller embedded version of the Vector extension
Having 32x 32 bit registers with LMUL=4, giving 8x 128 bits - does this allow for 64-bit elements?
I don't think it does, but it’s not clear in the spec.
I use 64-bit elements for “wide” and “quad” accumulators.
From: tech-vector-ext@... [mailto:tech-vector-ext@...] On Behalf Of Bruce Hoult
Sent: 02 June 2021 11:19
To: Tariq Kurd <tariq.kurd@...>
Cc: tech-vector-ext@...; Shaofei (B) <shaofei1@...>
Subject: Re: [RISC-V] [tech-vector-ext] Smaller embedded version of the Vector extension
There is nothing to prevent implementing 32x 32 bit registers on a 32 bit CPU. The application processor spec has quite
recently (a few months) specified a 128 bit minimum register size but I don't think there's any good reason for this,
especially in embedded.
With that configuration, LMUL=4 gives 8x 128 bits, the same as MVE.
If floating point is desired then Zfinx is available, sharing int & fp scalar registers instead of fp and vector registers.
Of course profiles (or just custom chips for custom applications) can define subsets of instructions.
On Wed, Jun 2, 2021 at 10:05 PM Tariq Kurd via lists.riscv.org <tariq.kurd=huawei.com@...> wrote: