Re: Smaller embedded version of the Vector extension

Tony Cole

Having 32x 32 bit registers with LMUL=4, giving 8x 128 bits - does this allow for 64-bit elements?

I don't think it does, but it’s not clear in the spec.


I use 64-bit elements for “wide” and “quad” accumulators.



From: tech-vector-ext@... [mailto:tech-vector-ext@...] On Behalf Of Bruce Hoult
Sent: 02 June 2021 11:19
To: Tariq Kurd <tariq.kurd@...>
Cc: tech-vector-ext@...; Shaofei (B) <shaofei1@...>
Subject: Re: [RISC-V] [tech-vector-ext] Smaller embedded version of the Vector extension


There is nothing to prevent implementing 32x 32 bit registers on a 32 bit CPU. The application processor spec has quite

recently (a few months) specified a 128 bit minimum register size but I don't think there's any good reason for this,

especially in embedded.


With that configuration, LMUL=4 gives 8x 128 bits, the same as MVE.


If floating point is desired then Zfinx is available, sharing int & fp scalar registers instead of fp and vector registers.


Of course profiles (or just custom chips for custom applications) can define subsets of instructions.


On Wed, Jun 2, 2021 at 10:05 PM Tariq Kurd via <> wrote:

Hi everyone,


Are there any plans for a cut-down configuration of the vector extension suitable for embedded cores? It seems that the 32x128-bit register file is suitable for application class cores but it very large for embedded cores, especially if the F registers also need to be implemented (which I think is the case, unless a Zfinx version is specified).


ARM MVE only has 8x128-bit registers for FP and Vector, so it much more suitable for embedded applications.


What’s the approach here? Should embedded applications implement the P-extension instead?




Tariq Kurd

Processor Design I RISC-V Cores, Bristol

E-mail: Tariq.Kurd@...

Company: Huawei technologies R&D (UK) Ltd I Address: 290 Park Avenue, Aztec West, Almondsbury, Bristol, Avon, BS32 4TR, UK      



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