Re: Smaller embedded version of the Vector extension

Guy Lemieux

On Wed, Jun 2, 2021 at 8:38 AM Andrew Waterman <andrew@...> wrote:
It’s actually not fundamental to the ISA design that VLEN >= ELEN. An implementation with VLEN=32 could support SEW=64 whenever LMUL >= 2. 

I think the concern here is lack of a clearly defined data layout pattern for such cases.

eg, should the LSBs be in the odd or even register half, or should it be implementation-defined?


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