| On Wed, Jun 2, 2021 at 8:38 AM Andrew Waterman <andrew@...> wrote:On Wed, 2 Jun 2021 08:41:52 -0700, "Guy Lemieux" <guy.lemieux@...> said:
| It’s actually not fundamental to the ISA design that VLEN >= ELEN. An
| implementation with VLEN=32 could support SEW=64 whenever LMUL >= 2.
| I think the concern here is lack of a clearly defined data layout pattern for
| such cases.
| eg, should the LSBs be in the odd or even register half, or should it be