Software should still work with VLEN>=64 if written correctly, as it should be VLEN agnostic.
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Maybe it should be a recommendation that VLEN>=128, with a minimum of 64 for app processors?
Lower performance is an implementation cost/benefit decision.
From: tech-vector-ext@... [mailto:tech-vector-ext@...] On Behalf Of Krste Asanovic
Sent: 03 June 2021 17:24
To: Guy Lemieux <guy.lemieux@...>
Cc: Andrew Waterman <andrew@...>; Tariq Kurd <tariq.kurd@...>; Shaofei (B) <shaofei1@...>; tech-vector-ext@...
Subject: Re: [RISC-V] [tech-vector-ext] Smaller embedded version of the Vector extension
On Jun 3, 2021, at 9:16 AM, Guy Lemieux <guy.lemieux@...> wrote:
What is the advantage to RVV requiring VLEN >= 128?
I think this should be changed to VLEN >= 64 because:
1) VLEN = 64 is more likely for small implementations; creating a
mandatory expectation to improve software portability
This is the requirement for app processors, which are not generally small cores.
Most competing SIMD extensions are at least 128b per vector register.
2) two implementations, each with VLEN >= 64, do not expose anything
new to software that is not already exposed by VLEN >= 128
3) allowing VLEN =32 would expose something new to software (register
file data layout when SEW=64)
4) are there any disadvantages to VLEN >= 64 (versus the current VLEN
= 128)? (I can't see any)
Lower performance on codes that work well on other app architectures.
On Wed, Jun 2, 2021 at 11:13 AM <krste@...> wrote:
The VLEN>=128 constraint is only for the application processor "V"
extension for the app profile - not for embedded vectors which can
From spec Introduction:
The term base vector extension is used informally to describe the standard set of vector ISA components that will be required for the single-letter "V" extension, which is intended for use in standard server and application-processor platform profiles. The set of mandatory instructions and supported element widths will vary with the base ISA (RV32I, RV64I) as described below.
Other profiles, including embedded profiles, may choose to mandate only subsets of these extensions. The exact set of mandatory supported instructions for an implementation to be compliant with a given profile will only be determined when each profile spec is ratified. For convenience in defining subset profiles, vector instruction subsets are given ISA string names beginning with the "Zv" prefix.
There are a set Zve* names for the embedded subsets (see github issue
A minimal embedded implementaton using RV32E+Zfinx+vectors would be
same state size as ARM MVE.
P extension does not have floating-point, but for short
integer/fixed-point SIMD makes sense as alternative.
The software fragmentation issue is that some library routines that
expose VLEN might not be portable between app cores and embedded
cores, but these are different software ecosystems (e.g. ABI/calling
convention might be different) and only a few kinds of routine rely
For app cores that can afford VLEN>=128, the advantage is the removal
of stripmining code in cases that operate on fixed-size vectors.
| Allowing VLEN<128 would allow for smaller vector register files,
On Wed, 2 Jun 2021 05:10:32 -0700, "Guy Lemieux" <guy.lemieux@...> said:
| bit it would also result in a profile that is not
| forward-compatible with the V spec. This would produce another fracture the software ecosystem.
| To avoid such a fracture, there are two choices:
| (1) go with P instead
| (2) relax the V spec to allow smaller implementations
| So the key question for this group is whether to relax the minimum
| VLEN to 32 or 64?
| note: a possible justification for keeping 128 might be to
| recommend (1) instead. I don’t know anything about P, but it seems
| like it could be speced in a way that is competitive/comparable with Helium.
| PS — I have started to design an “RVV-lite” profile which would be
| more amenable to embedded implementations. However, I have adopted
| a stance that it must remain forward compatible with the full V
| spec, so I have not considered VLEN below 128. I am happy to share
| my work on this and involve other contributors — email me if you would like to see a copy.
| On Wed, Jun 2, 2021 at 3:15 AM Andrew Waterman <andrew@...> wrote:
| The uppercase-V V extension is meant to cater to apps processors, where
| the VLEN >= 128 constraint is not inappropriate and is sometimes
| beneficial. But there's nothing fundamental about the ISA design that
| prohibits VLEN < 128. A minimal configuration is VLEN=ELEN=32, giving the
| same total amount of state as MVE. (And if you set LMUL=4, then you even
| get the same shape: 8 registers of 128 bits apiece.)
| Such a thing wouldn't be called V, but perhaps something like Zvmin.
| Other than agreeing on a feature set and assigning it a name, the
| architecting is already done.
| (If you search the spec for Zfinx, you'll see that a Zfinx variant is
| planned, but only barely sketched out.)
| On Wed, Jun 2, 2021 at 3:04 AM Tariq Kurd via lists.riscv.org <tariq.kurd=
| huawei.com@...> wrote:
| Hi everyone,
| Are there any plans for a cut-down configuration of the vector
| extension suitable for embedded cores? It seems that the 32x128-bit
| register file is suitable for application class cores but it very
| large for embedded cores, especially if
| the F registers also need to be implemented (which I think is the
| case, unless a Zfinx version is specified).
| ARM MVE only has 8x128-bit registers for FP and Vector, so it much
| more suitable for embedded applications.
| What’s the approach here? Should embedded applications implement the
| P-extension instead?
| Tariq Kurd
| Processor Design
| I RISC-V Cores, Bristol
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