I did not expect that this meeting, of all meetings, would be cancelled.

So I’ll send my comments by email now rather than discussing an important one at the meeting and filing issues for minor ones.  I think #1 is important.  The rest are lesser comments:

1. I’m (still) concerned about the lack of a whole register load with “mask” type hint.  I think leaving it out damages the clarity of support for micro-architectural redistribution, which is critical for wide SIMD.
• If we really will not add the instruction, I’m thinking there’s a relatively simple sequence that does the job, like save vl, set it to max, do an ordinary mask load, restore vl.  Could you add that sequence somewhere.  Maybe in the note about not having the mask version.  That would help make the completeness of support clear for micro-architectural redistribution.
2. In Section 3.5, I’m not sure why vlenb must be a design-time constant.  An implementation could vary it as a mode.  So, I think the wording should allow that.
3. Section 13.19 has a typo.  It says “widening” when I think it means “narrowing.”
4. In Section 14, what is the thinking on why there’s no update of the destination of reductions when vl=0?  I can’t see any reason not to update – it seems easier to update – and it could, in some circumstances matter.  This rule means that code has to ensure that it does not execute a reduction in a rare case that vl might be zero unless the source scalar and destination scalar are the same register.  Why require that?
5. In Section 7.8, I thought we wanted the set of registers a segment load/store could access to be limited to an aligned group of eight to allow optimizations on the renaming of registers.  So a three register group could start at register #3, for example.  But here it says that a sequence can start anywhere.

    Bill