On Sun, Sep 19, 2021 at 11:39 AM Jim Wilson <jimw@...> wrote:

On Sat, Sep 18, 2021 at 3:57 PM Mick Thomas Lim <mickthomaslim@...> wrote:

Alternatively, how is everyone running v1p0 programs on v1.0 qemu?
We'd like to adhere as closely to the latest Vector ext. revision as possible.

In general, I'd say that if you don't have a half dozen people doing assembler, compiler, simulator, kernel, library, etc work, then you probably won't be able to create your own V environment. Unfortunately SiFive doesn't have a free V distribution anymore. And no, the freedom-u-sdk V support isn't useful. I would suggest that PLCT is your best bet. See Wei Wu's message pointing your at binutils, gcc, and qemu trees. Except Wei Wu pointed at gcc and the gcc V support is known to have problems, so is not a good choice. So there is probably no free good V environment available at this time.

That's true. :)

Providing full support for Vector extension is already on the todo-list of
CAS/PLCT Lab.

Vector extension is one of the extensions that are included in an
all-in-one developer environment project in PLCT Lab. If one extension
is not ready, we will implement it first. And given that the v1.0 tag has just
been tagged[1], it is a good time to start :)

There was a working branch for V-ext in riscv-gnu-toolchain repo
maintained by SiFive staff, and unfortunately SiFive does not have enough
GCC developers for maintaining it to keep it up to date with the
latest draft. I've talked with Kito who is working on Vector impl for
GNU toolchain, and he welcomes us working on it. The PLCT Lab has set
a few CI/Testing jobs watching the public V-ext branch already, and plans to
start the upgrading work after the initial all-in-one environment for
developers release.

A developer from Alibaba/T-Head is working on V-ext on GCC. Although
T-Head is working on the v0.7.1 draft version, the developer from
T-Head has contributed a few patches for the latest drafts. I'm optimistic
that at least one SiFive staff and one T-Head staff will contribute in
their spare time.

A more ambitious plan is to implement an open source RISC-V core with
B/K/P/V-ext enabled, using Chisel as the impl language. It is only an
idea in my head now, and currently no staff in PLCT Lab is working on it
(a few interns may start the project next month). I'd like to provide help on
software support if there is another team willing to work on it.

[1] https://github.com/riscv/riscv-v-spec/releases/tag/v1.0

--
Best wishes,
Wei Wu (吴伟)