Re: RISC-V Vector Extension post-public review updates

Guy Lemieux

That’s great news, thanks Krste!

The current specification allows some instructions to have two vector
source operands read from the same vector register but with different

(cue folks furiously trying to construct one...)

haha i tried but can’t think of a use case !!

We do have a choice of:

1) Mandate all implementations raise an illegal exception in this
case.  This is my preferred route, as this would be a minor errata for
existing implementations (doesn't affect software), and we would not reuse
this state/encoding for other purposes.

2) Allow either correct execution or illegal exception (as with

3) Consider "reserved", implying implementations that support it are
non-conforming unless we later go with 2).

I don’t have a strong opinion, but I prefer a route that allows us to recover those instruction encodings — they seem to be getting scarce hence represent value. You said there were already requests for extra instructions — would this space be usef for any of them (or other as-yet-unforeeen instructions)?

Does (3) give us the best route to reuse the encodings in the future? I’m a bit confused about the permanence of (1), and I don’t like the possibility software fragmentation that will arise from (2).


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