Re: RISC-V Vector Extension post-public review updates
From: Andrew Waterman <andrew@...>
Sent: Monday, November 15, 2021 5:32 PM
To: Bill Huffman <huffman@...>
Cc: Krste Asanovic <krste@...>; Guy Lemieux <guy.lemieux@...>; tech-vector-ext@...
Subject: Re: [RISC-V] [tech-vector-ext] RISC-V Vector Extension post-public review updates
On Mon, Nov 15, 2021 at 2:17 PM Bill Huffman <huffman@...> wrote:
I think these encodings are qualitatively different from other nooks and crannies, since their availability is a function of the dynamic vtype setting. So we can rationalize the departure from the normal practice of marking the state reserved.
Other nooks and crannies are also dependent on vtype. For example, widening instructions are not valid for LMUL large enough to make the wider operands cover more than 8 registers.
I'd personally prefer #3 due to laziness, but I don't have a technical objection to #1.