Re: RISC-V Vector Extension post-public review updates


Krste Asanovic
 

On Tue, 16 Nov 2021 17:15:28 +0000, Bill Huffman <huffman@...> said:
| From: Grigorios Magklis <grigorios.magklis@...>
| Sent: Tuesday, November 16, 2021 12:03 PM

| What is the thinking for when we go to >32-bit encodings with respect to vtype
| and masks? I assume that the longer encoding could encode SEW (and LMUL?) as
| an override of vtype. What about masks though? If we enable more than one
| masks (m0…mN) in 48-bit/64-bit encodings, and we want to mix 32-bit and 48-bit
| /64-bit instructions in the same code, do we still specify that e.g. m0==v0 or
| do we need to explicitly copy v0 to e.g. m0 before it can be used with 48-bit/
| 64-bit instructions (and vice versa when switching from 48-bit/64-bit
| instructions to 32-bit instructions)? It would be nice if we could reclaim v0
| (actually v0 through v7 for LMUL=8) from being a mask to being able to hold
| data, *and* not to have to force the whole code/loop body to use 48-bit/64-bit
| instructions in order to do this.

| Grigorios

My thinking for longer encoding is we would not add different mask
registers, but instead possibly expand set of architectural vector
registers.

| I don’t think there’s any agreement at this point on what goes into a longer
| instruction, but there are a number of candidates, including at least:

| ● LMUL
| ● SEW
| ● VMA and VTA bits
| ● Register specifier for the mask register
| ● Additional registers – perhaps 128 instead of 32
| ● Possibly a fourth register specifier (not counting mask).

| If I’m counting correctly, that’s already 28 additional bits. That’s in the
| range of the maximum that can be put into a 64-bit instruction set. There are
| probably more candidates and discussion about which ones to include will
| certainly be needed. 😊

Right, even 64 bits will seem tight if all wishes are considered.
Some more experience with actual code and compilers is needed to help
tune future extensions.

Krste

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