Re: RISC-V Vector Extension post-public review updates

Krste Asanovic

On Nov 17, 2021, at 10:43 AM, Bill Huffman <huffman@...> wrote:
-----Original Message-----
From: krste@... <krste@...> 
Sent: Wednesday, November 17, 2021 1:02 PM
To: Bill Huffman <huffman@...>
Cc: Grigorios Magklis <grigorios.magklis@...>; tech-vector-ext@...
Subject: RE: [RISC-V] [tech-vector-ext] RISC-V Vector Extension post-public review updates
My thinking for longer encoding is we would not add different mask registers, but instead possibly expand set of architectural vector registers.
Does that mean continuing to assume fusing a mask move with an instruction where desired?

Not necessarily with a larger mask register specifier. For example, with 3b mask register specifier, we could expand to encode v0-v6 as mask sources with 111 meaning unmasked.


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