Re: RISC-V Vector Extension post-public review updates
On 2021-11-17 4:32 p.m., Bill Huffman wrote:
I am curious as well.
It makes sense when the whole vector is participating and masking
is the only means to limit processing, but we have vlen.
Specifically no First Fault variant was included so that a single instruction could not capture large swaths of the memory map information.
Of course no faulting but flagging would be even worse.