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- The Width of vcsr and vstart
Re: The Width of vcsr and vstart
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For the current V extension, it's correct to treat both vcsr and vstart as 32-bit registers. I agree the spec should clearly indicate whether or not these registers will always be 32 bits (like fcsr).
Debuggers can use abstract commands to access CSRs. When using abstract commands, debuggers need to specify the bit width of CSRs. The bit widths of vcsr and vstart are not clearly defined in Vector Extension version1.0. In an RV64 implementation, The debugger is not clear whether the bit width of these two CSRs should be regarded as 32 or 64. May be we need specify the bit width of these CSRs in the spec, XLEN or fixed-length 32bit.
The fcsr defined in RISC-V Unprivileged ISA is fixed-length 32bit CSR. The register structure of vcsr is similar to fcsr.So maybe vcsr should also be defined as a fixed-length 32bit register?
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