Re: [RISC-V] [tech-unprivileged] [RISC-V] [tech-vector-ext] FP Trapped exceptions needed for portability
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IF the Trap-on-masked-fflags op isn't executed often, then a 4 instruction sequence
(CSRRD FFLAGS, ANDI, BNE, .+4, ECALL) would do that, so there is a workaround.
IF that has a performance impact, then it argues that you may need actual trapping behavior.
On Fri, Dec 17, 2021 at 5:05 PM ghost <ghost@...> wrote:
> I’d suggest identifying important use cases for this. I’d also be looking at