about masked-off bits for instructions vmsbf.m, vmsif.m, vmsof.m #defines


I have a question about masked-off bits. 
I am not sure what is the behavior of destination inactive masked-off bits for instructions vmsbf.m, vmsif.m, vmsof.m. Does the "xxxx" means we can fill any value to these bits, regardless of vtype.vma? 
I copied the example codes below, which is from section 15.4 of RVV spec 1.0 frozen:
1 1 0 0 0 0 1 1 v0 vcontents
1 0 0 1 0 1 0 0 v3 contents
                       vmsbf.m v2, v3, v0.t
0 1 x x x x 1 1  v2 contents
In addition, whether all mask-result instructions need to fill the mask-off bits according to the vtype.vma policy, such as vector integer compare instructions?
And is it allowed that the implementation choose to only support mask-agnostic and tail-agnostic for mask-result instructions?

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