1. Question for tail bits of mask-producing instructions.

In the case of mask-producing instructions, tail elements are the bits with (vl <= bit index < VLEN).So according to riscv-v-spec-1.0, page 46, VMADC/VMSBC instructions operate with tail-agnostic policy, which means the tail bits can be written with 1 or unchanged. 

While according to page 13, we have a more relax constraint: except for mask load instructions, any element in the tail of a mask result can also be written with the value the mask-producing operation would have calculated with vl=VLMAX. Which means we can overwritten all remaining bits that past vl with 1s or with the value the mask-producing operation would have calculated.

For example, if VLEN=128, LMUL=1, SEW=32, there are only 4 body bits for VMADC instruction. If current vl=2, we can write the calculation results to bit[1:0], and write all other 126 bits with 1s. Or we can write 4 bits calculation results to bit[3:0] in which only bit[1:0] are body bits, and write all other 124 bits with 1s.

Whether either of these implementations is legal?

 

2. Question for inactive body bits of mask-producing instructions.

When vtype.vma=0, which means mask-undisturbed policy, the inactive body bits should retain its value. 

For example, when vma=0, the VMSBF_M and VMSEQ with vm=0, should not change the inactive body bits.

Is my understand correct?thanks.