I applaud the ordinal nature of the mask structure that is independent of SEW and LMUL. The problem that I have is the mismatch between units of measure, which is bytes in element lengths and bits in

We’ll be meeting tomorrow morning. Meeting details on member calendar. Krste (on iPhone, forgive terseness)

Right, now there’s just a single blanket statement that no vector instruction can overwrite the mask register Krste (on iPhone, forgive terseness)

Never mind, I misread the git commit log. It appears that no instructions can overwrite the mask register. Sorry.

Hi Krste, It seems that many (all?) masked instructions are now allowed to overwrite the mask register. This new scheme would indeed be simpler --- is this true? Can you give any high-level insight

I've made a major update to mask encoding, pushed to repo. The earlier change to support fractional LMUL effectively "broke" the earlier mask encoding. The new scheme is simpler, but is

PS: Instead of loading the RHS entries with an indexed load, we could also use a unit-stride load (possibly masked), followed by a vcompress. This didn't seem like a clear win, and required additional

Hi Nagendra, The goal of the Zvediv extension is to add some support for sub-byte datatypes. So my hope is that applications that use bitvectors to encode nonzero structure will be supported via

sorry I wasn’t clear. the data types, eg vint64m1_t, are for data elements. all of the example API definitions also use these same element data types as arguments, but they should be using a data

On Thu, May 7, 2020 at 07:28 PM, Kai Wang wrote: On Fri, May 8, 2020 at 1:47 AM Guy Lemieux <glemieux@...> wrote: well done! can you perhaps explain how the vector operands are to be

How many registers will be used for a type depends on the LMUL for the type when LMUL >= 1. For example, vint32m1_t will occupy one register and vint16m2_t will occupy two registers and the register

I am now investigating how to efficiently implement sparse matrix X (dense) vector multiplications (spMV) using RISCV vectors using bit-vector format of compressing the sparse matrix. The inner loop

well done! can you perhaps explain how the vector operands are to be used/allocated? ie, it appears you wish to use the type system to name vector registers, but there is no limit on these so there

Hi, We, EPI, SiPearl, and SiFive, have come out with a RFC for vector intrinsics. Although there are still some issues under discussion, we think it is time to publish the document to collect more

I pushed an update to spec that includes the sign/zero-extension instructions so now can hopefuly answer this question more concretely. The point of fractional LMUL is to reduce register usage, so

Hi Krste, On the SLEN=VLEN discussion, I agree with you that using a cast instruction might well make for a de facto split in the code base. But I don't think the solution is to force a de jure

BTW, even if overlapping of source/destination registers is not an issue, would the use of fractional LMUL to load data, would it still be 2 extra instructions in the loop to change from fractional

Hi All, The issue that I brought up about the extra register that is needed to load data with LMUL=8 and then signed/unsigned extension that would need an extra register. I am still puzzled/confused

Note: To help understand the #423 as the meeting introduction only mentioned transient SEW and LMUL overrides. The proposal is generalized and includes extending modifiers beyond what are mapped by

Date: 2020/5/1 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues