tech-vector-ext@lists.riscv.org

Home Messages Hashtags Subgroups

Messages

Topics Expanded

Export Group Data

Between

and

Re: Vector Task Group minutes 2020/5/15

You're absolutely right. Thanks for the correction.

By Roger Espasa · #187 ·

Re: Vector Task Group minutes 2020/5/15

On 2020-05-29 6:18 a.m., Roger Espasa wrote: The very significant correction is that for v09 SLEN=VLEN memory ordering IS preserved for LMUL>1 should be

By David Horner · #186 ·

Re: Vector Task Group minutes 2020/5/15

I was trying to summarize/compare the different proposals. I talked to Grigoris and I think this is a correct summary: v08 v09 Grigoris LMUL=1 SLEN=VLEN SLEN does not matter SLEN

By Roger Espasa · #185 ·

Vector TG Meeting Friday May 29

Reminder we have our TG meeting this Friday morning. Details on member calendar. Krste

By Krste Asanovic · #184 ·

Re: Vector Task Group minutes 2020/5/15

Guy, FPGA energy/power data is not really relevant to general purpose ISA design, unless your goal is to design an ISA only for soft FPGA cores like Nios or MicroBlaze. Please, take a look at the

By Alex Solomatnikov · #183 ·

Re: Vector Task Group minutes 2020/5/15

Alex, Keep in mind: a) I amended my proposal to reduce the code bloat identified by Nick b) the effect of the bloat is almost entirely about text segment size, not power or instruction bandwidth,

By Guy Lemieux · #182 ·

Re: Vector Task Group minutes 2020/5/15

Code bloat is important - not just the number load and store instructions but also additional vsetvl/i instructions. This was one of the reasons for vle8, vle16 and others. LMUL>1 is also great for

By Alex Solomatnikov · #181 ·

Re: Vector Task Group minutes 2020/5/15 - CLSTR for in-register to in-memory alignment

I made this into its own thread as well. I think there is a parallel in the in-register/in-memory issue and memory consistency model/methods. The complexity of consistency models

By David Horner · #180 ·

Re: Vector Task Group minutes 2020/5/15 - V0.8 design with SLEN=8

I seem to recall that at some point LMUL was only a suggestion and that if the requested vl was short (e.g. the last strip-mining loop on a long application vector) the vsetvl[i] instruction was free

By Bruce Hoult · #179 ·

Re: Vector Task Group minutes 2020/5/15 - V0.8 design with SLEN=8

I have some suggestions for the reasons for moving from v0.8 vertical striping to v0.9 horizontal SLEN (interleave) Under v0.8 A) when vl < VLEN/SEW*LMUL the top elements are not

By David Horner · #178 ·

Re: Vector Task Group minutes 2020/5/15 - precise layout not matter

I propose 2 data layouts: memory layout, and internal register group layout. I am not going to specify which internal register group layout to operate upon, because I haven't read the 0.9 spec and

By Guy Lemieux · #177 ·

Re: Vector Task Group minutes 2020/5/15 - precise layout not matter

On 2020-05-27 7:58 p.m., Guy Lemieux wrote: I believe this can be weakened to required: select-able distribution patterns that are sufficiently compatible that they

By David Horner · #176 ·

Re: Vector Task Group minutes 2020/5/15

Hi Guy, Thanks for your reply. I'll leave a few quick responses, and would like to hear opinions from others on the task group. Agreed. Agreed, especially regarding code storage. When loop

By Nick Knight · #175 ·

Re: Vector Task Group minutes 2020/5/15

Nick, thanks for that code snippet, it's really insightful. I have a few comments: a) this is for LMUL=8, the worst-case (most code bloat) b) this would be automatically generated by a compiler, so

By Guy Lemieux · #174 ·

Re: Vector Task Group minutes 2020/5/15

I appreciate this discussion about making things friendlier to software. I've always felt the constraints on SLEN-agnostic software to be a nuisance, albeit a mild one. However, I do have a concern

By Nick Knight · #173 ·

Re: Vector Task Group minutes 2020/5/15

The precise data layout pattern does not matter. What matters is that a single distribution pattern is agreed upon to avoid fragmenting the software ecosystem. With my additional restriction, the

By Guy Lemieux · #172 ·

Re: Vector Task Group minutes 2020/5/15

This is v0.8 with SLEN=8.

By David Horner · #171 ·

Re: Vector Task Group minutes 2020/5/15

for those not on Github I posted this to #461: CLSTR can be considered a progressive SLEN=VLEN switch. Rather than all or nothing as the SLEN=VLEN switch provides for in-memory

By David Horner · #170 ·

Re: Vector Task Group minutes 2020/5/15

As a follow-up, the main goal of LMUL>1 is to get better storage efficiency out of the register file, allowing for slightly higher compute unit utilization. The memory system should not require LMUL>1

By Guy Lemieux · #169 ·

Re: Vector Task Group minutes 2020/5/15

I support this scheme, but I would further add a restriction on loads/stores to only support LMUL=1 (no register groups). Instead, any data stored in a registe group with LMUL!=1 must first be

By Guy Lemieux · #168 ·

701 - 720 of 887

Home Hashtags Subgroups Terms