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Re: Issue #365 vsetvl{i} x0, x0 instruction forms
I agree with Krste's support for Guy's proposal here. Loops with
multiple element widths are likely to have more non-vl-changing
instructions than vl-changing instructions. Knowing this from the
I agree with Krste's support for Guy's proposal here. Loops with
multiple element widths are likely to have more non-vl-changing
instructions than vl-changing instructions. Knowing this from the
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By
Bill Huffman
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#285
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Re: Issue #365 vsetvl{i} x0, x0 instruction forms
The main issue is whether the current PoR has any useful purpose when
vl changes. I don't subscribe to "field of dreams" approach. I tried
to find some scenarios hoping there would be some useful
The main issue is whether the current PoR has any useful purpose when
vl changes. I don't subscribe to "field of dreams" approach. I tried
to find some scenarios hoping there would be some useful
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By
Krste Asanovic
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#284
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Re: Issue #365 vsetvl{i} x0, x0 instruction forms
I wholeheartedly agree with resolving on the mailing list.
This should be the rule not exception.
My considerations for allowing vl to change were
a) having a compelling reason to change
I wholeheartedly agree with resolving on the mailing list.
This should be the rule not exception.
My considerations for allowing vl to change were
a) having a compelling reason to change
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By
David Horner
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#283
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Issue #365 vsetvl{i} x0, x0 instruction forms
I want to bring this to group's attention as I think I've convinced
myself that Guy's suggestion is the correct path to follow, i.e.,
vsetvli x0, x0, imm
will raise vill if the new SEW'/LMUL'
I want to bring this to group's attention as I think I've convinced
myself that Guy's suggestion is the correct path to follow, i.e.,
vsetvli x0, x0, imm
will raise vill if the new SEW'/LMUL'
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By
Krste Asanovic
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#282
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Re: Duplicate Counting Instruction
Hi,
Sorry the picture was dropped somehow, here I can present using pure text:
For the simple loop example:
for (i = 0; i < N; i++) {
a[b[i]] = a[c[i]] + 1;
}
We can use the algorithm:
while (i +
Hi,
Sorry the picture was dropped somehow, here I can present using pure text:
For the simple loop example:
for (i = 0; i < N; i++) {
a[b[i]] = a[c[i]] + 1;
}
We can use the algorithm:
while (i +
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By
lidawei14@...
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#281
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Re: [riscv/riscv-v-spec] For V1.0 - Make unsigned scalar integer in widening instructions 2 * SEW (#427) (and signed)
This was on Github; as not every one subscribes and it will be considered at TG, I include it on this list.
First Krste’s synopsys, then my (modified) Github reply,
This was on Github; as not every one subscribes and it will be considered at TG, I include it on this list.
First Krste’s synopsys, then my (modified) Github reply,
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By
David Horner
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#280
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Vector Task Group minutes 2020/7/17
Date: 2020/7/17
Task Group: Vector Extension
Chair: Krste Asanovic
Co-Chair: Roger Espasa
Number of Attendees: ~20
Current issues on github: https://github.com/riscv/riscv-v-spec
Issues
Date: 2020/7/17
Task Group: Vector Extension
Chair: Krste Asanovic
Co-Chair: Roger Espasa
Number of Attendees: ~20
Current issues on github: https://github.com/riscv/riscv-v-spec
Issues
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By
Krste Asanovic
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#279
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CORRECTION, minutes from 2020/07/10 meeting
I managed to swap the file names around, and sent earlier week's
minutes instead of last week's. Here's the correct minutes from last
week (also fixed in repo).
Krste
Date: 2020/7/10
Task Group:
I managed to swap the file names around, and sent earlier week's
minutes instead of last week's. Here's the correct minutes from last
week (also fixed in repo).
Krste
Date: 2020/7/10
Task Group:
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By
Krste Asanovic
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#278
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minutes from last meeting
A belated posting of minutes from last week's meeting.
We'll be meeting again today as per member calendar,
Krste
Date: 2020/7/03
Task Group: Vector Extension
Chair: Krste Asanovic
Co-Chair: Roger
A belated posting of minutes from last week's meeting.
We'll be meeting again today as per member calendar,
Krste
Date: 2020/7/03
Task Group: Vector Extension
Chair: Krste Asanovic
Co-Chair: Roger
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By
Krste Asanovic
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#277
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Re: VFRECIP/VFRSQRT instructions
Excellent observation.
at least 1 bits better. and when r*x close to 1, much better.
Excellent observation.
at least 1 bits better. and when r*x close to 1, much better.
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By
David Horner
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#276
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Re: VFRECIP/VFRSQRT instructions
Yes.
By
andrew@...
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#275
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Re: VFRECIP/VFRSQRT instructions
Do we improve accuracy a bit if the step is:
t = 1.0 - r*x; x = x + t*x
instead of:
t = 2.0 - r*x; x = t*x
Bill
On 7/14/20 2:58 PM, Bill Huffman wrote:
Do we improve accuracy a bit if the step is:
t = 1.0 - r*x; x = x + t*x
instead of:
t = 2.0 - r*x; x = t*x
Bill
On 7/14/20 2:58 PM, Bill Huffman wrote:
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By
Bill Huffman
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#274
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Re: VFRECIP/VFRSQRT instructions
On 7/14/20 2:54 PM, Andrew Waterman wrote:
Sorry, I had scalar on the mind....
Bill
On 7/14/20 2:54 PM, Andrew Waterman wrote:
Sorry, I had scalar on the mind....
Bill
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By
Bill Huffman
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#273
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Re: VFRECIP/VFRSQRT instructions
Actually, none of the vector instructions use the rs3 field (the vector FMAs are destructive to save encoding space).
There are still several R-type code points left in the vector opcode, but it has
Actually, none of the vector instructions use the rs3 field (the vector FMAs are destructive to save encoding space).
There are still several R-type code points left in the vector opcode, but it has
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By
andrew@...
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#272
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Re: VFRECIP/VFRSQRT instructions
On 7/14/20 2:30 PM, Andrew Waterman wrote:
Seems like they shouldn't be so big as they don't specify rs3 at all. Are we tight on two register input opcodes?
Bill
On 7/14/20 2:30 PM, Andrew Waterman wrote:
Seems like they shouldn't be so big as they don't specify rs3 at all. Are we tight on two register input opcodes?
Bill
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By
Bill Huffman
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#271
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Re: VFRECIP/VFRSQRT instructions
FWIW, one of my concerns with adding the "step" instructions is opcode space, since we are already very tight. I suppose a compromise might be to make them destructive. This would have no perf.
FWIW, one of my concerns with adding the "step" instructions is opcode space, since we are already very tight. I suppose a compromise might be to make them destructive. This would have no perf.
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By
andrew@...
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#270
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Re: VFRECIP/VFRSQRT instructions
I forgot to mention that I added sample vector code for estimating square root: https://github.com/riscv/riscv-v-spec/blob/vfrecip/vector-examples.adoc#square-root-approximation-example
Handling the
I forgot to mention that I added sample vector code for estimating square root: https://github.com/riscv/riscv-v-spec/blob/vfrecip/vector-examples.adoc#square-root-approximation-example
Handling the
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By
andrew@...
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#269
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Re: VFRECIP/VFRSQRT instructions
Hi Andrew et al,
Thank you for sending the code. I am attaching an updated version of recip.cc, implementing the complete Newton-Raphson sequence, using the proposed reciprocal estimate instructions
Hi Andrew et al,
Thank you for sending the code. I am attaching an updated version of recip.cc, implementing the complete Newton-Raphson sequence, using the proposed reciprocal estimate instructions
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By
Mr Grigorios Magklis
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#268
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Re: VFRECIP/VFRSQRT instructions
I've updated the proposal to describe the corner cases:
https://github.com/riscv/riscv-v-spec/blob/vfrecip/v-spec.adoc#149-vector-floating-point-reciprocal-estimate-instruction
I've updated the proposal to describe the corner cases:
https://github.com/riscv/riscv-v-spec/blob/vfrecip/v-spec.adoc#149-vector-floating-point-reciprocal-estimate-instruction
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By
andrew@...
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#267
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Vector TG meeting
We’ll have our regular TG meeting in a few hours per member calendar.
We’ll continue to clean up remaining issues for v1.0,
Krste
We’ll have our regular TG meeting in a few hours per member calendar.
We’ll continue to clean up remaining issues for v1.0,
Krste
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By
Krste Asanovic
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#266
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