Hi,  We met some problems as your mention also.  Consider some code will want args in vector regs, we study from SVE    vregs layout and config our RISCV vregs layout as following:  | v0-7

Some code will not want args in vector regs, so that we don't have to save/restore them around calls. Some code will want args in vector regs, so that they can have subroutines that operate on

Vectors are passed in memory and returned in memory. Vectors are arbitrary length, whereas the vector registers are fixed length, and can only be used to temporarily hold a portion of a memory vector.

Hi,  Thanks for your mention.  It’s so clear & simple, there is no convention for vector args & return of function ?    also, according our long time designed cpu experiments, there should

There is a brief sketch of the Linux vector calling convention here: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc Note this is the convention for normal C ABI calls; a

Hi,  Anyone know extra designed ABI information (like Calling Convention)    about for vector register ? --Jojo

Krste, Roger We have just released an update of our free riscvOVPsim reference simulator version: 20191217.0 and put it on the https://github.com/riscv/riscv-ovpsim. riscvOVPsim supports the full