Hi everyone, I’ve updated the Zfinx spec to show which V-extension instructions are affected. https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc#vector Please review the

For hardware with very long vector registers, the same effect might be accomplished by having a custom way to change VLMAX dynamically (across all harts, etc.). It would seem that would cover a

| in terms of overlap with that case — that case normally selects maximally sized AVL. the implied goals there are to make best use of vector register capacity and | throughput. l | i’m

in terms of overlap with that case — that case normally selects maximally sized AVL. the implied goals there are to make best use of vector register capacity and throughput. l i’m suggesting a

| I agree with you. | I had suggested the mapping of 00000 to an implementation-defined value (chosen by the CPU architect). For some architectures, this may be 16, for others it may | be 32, or even

I agree with you. I had suggested the mapping of 00000 to an implementation-defined value (chosen by the CPU architect). For some architectures, this may be 16, for others it may be 32, or even 2. The

Replying to old thread to add rationale for current choice. | Does it get easier if the specification is just the immediate value plus one? No - this costs more gates on critical path. Mapping

Try gitrhub.com/riscv/riscv-v-spec. There is also software stuff like riscv/rvv-intrinsic-doc that is defining compiler intrinsics for the vector spec. Like bitmanip, you can file issues or pull

Hello, I've just joined the RISC-V technical community and the V Extension Task group. I have very substantial experience in careful technical documentation (I wrote the RFCs for gzip and DEFLATE,

Date: 2021/02/05 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Next

We’ll meet tomorrow in usual slot per TG calendar. The agenda is to review any feedback on the 0.10 spec and then to proceed through any outstanding issues, Krste

Hi all, As part of the (first) annual process of holding elections for chairs of current Task Groups, this is a request for candidates for the chair and vice-chair positions in the Vector

Thanks Andrew, Bill, Krste, I've implemented this per our discussion.

I attempted to write a sequence that addresses that observation, along with a couple other pedantic details, and posted it to the ticket. https://github.com/riscv/riscv-v-spec/issues/623

Krste, I think the round float to integer as float sequence needs to use vmfle.vf with the usage of the mask inverted. Otherwise NaN values will use the integer instead of the original NaN.

Date: 2021/01/29 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec #

I cut a v0.10 release after adding all the substantial pending updates. There is still a bunch of work to do before public review, but this is a convenient milestone for toolchain developers, Krste

I scheduled next vector TG meeting tomorrow in usual slot with usual zoom link on TG Google calendar. I hope to push out updated spec sometime before then, Krste

Hi Krste - was this ever scheduled? thanks -- Jeffrey Osier-Mixon | jefro@... • jefro@... Linux Foundation | linuxfoundation.org • RISC-V International | riscv.org

I see it on riscv-v-spec commit: 0e8cdeb26bb98de2b1089d79a681af2c5a65e712 vmv.x.s belong to VWXUNARY0 and OPMVV But OPMVV has only vs1 no rs1, see : So i think `vmv.x.s rd, vs2 # x[rd] =