Hi, I’m starting a project where we want to use vector intrinsics and generate both 64b and 32b code (for RV64 and RV32). It looks line the best way to do this right now is with GCC, where we were

Yeah. I posted this link to our reddit /r/riscv four weeks ago and made a few comments about it. https://www.reddit.com/r/RISCV/comments/moz93r/arm_vs_riscv_vector_extensions/ It was posted on Hacker

I guess the publicity doesn't hurt, but I do wish the author had considered our developments here (at riscv/riscv-v-spec). His material appears to derive from Patterson-Waterman's 2017 book (and

https://erik-engheim.medium.com/arm-vs-risc-v-vector-extensions-992f201f402f Rather superficial - all about how hard it is for a person to program in assembly language, rather than how a compiler can

Hi Tony: Could you create issues on github to track that? https://github.com/riscv/riscv-gcc Thanks :)

I would suggest filing an issue in the riscv/riscv-gnu-toolchain github tree. Put something like vector or rvv in the issue title to make it clear it is a vector related issue. The gcc support is

Hi all, I’m still new to RISC-V and the Vector extensions, so forgive me if I’ve missed something, the following have been fixed or noted before. Also, am I sending this to the correct

Hi Vector Team, I’m new to RISC-V and the Vector extensions, so forgive me if I’ve missed something. I have searched the specs, emails and git hub issues, but not found anything on

I haven’t seen any burning issues come by, and am still trying to clean up spec. So unless someone has agenda items, I’m canceling meeting tomorrow, Krste

I’m still working on spec cleanup and I don’ t have any major outstanding issues to discuss, so will cancel the TG meeting this week. Please bring up any burning issues on this mailing

Date: 2021/03/26 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~10 Current issues on github: https://github.com/riscv/riscv-v-spec A short meeting

We'll meet again in usual slot. The main discussion topic will be #545. Please read the issue thread on github. Summary: The proposal is to move vector AMOs from their current encoding to leave

Date: 2021/03/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec Issues

There are a few issues to discuss, so we’ll meet in the regular time slot on the calendar, Krste

I'm cancelling meeting again, as I still have not been able to clean spec. I realize it will be more efficient for folks to wait for a clean version for a complete read through. Few issues are

I'm still working through spec cleanup. The list and github has been quiet, and I have no new issues to raise, so I suggest we cancel this meeting and push out for a week. Krste

Date: 2021/02/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~23 Current issues on github: https://github.com/riscv/riscv-v-spec # Next

Thanks Krste, I’ve put exactly that I the spec. Tariq From: tech-vector-ext@... [mailto:tech-vector-ext@...]On Behalf Of Krste Asanovic Sent: 18 February 2021 19:09 To: Tariq Kurd

We’ll meet today in usual slot, details on Google calendar Agenda is to discuss any issues found while reading over the v0.10 spec. List and GitHub has been quite quiet, so this might be a short

If you check over the vector instruciton listing table It’s all the instructions in funct3=OPFVF with an F in the operand column. Most of these are missing. Krste