
Re: Smaller embedded version of the Vector extension
If there was no cost, then supporting VLEN=64 on general apps
processor profile would be a good thing to do. But not allowing
standard software to assume VLEN>=128 imposes a nontrivial impact
If there was no cost, then supporting VLEN=64 on general apps
processor profile would be a good thing to do. But not allowing
standard software to assume VLEN>=128 imposes a nontrivial impact

By
Krste Asanovic
·
#639
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Re: Smaller embedded version of the Vector extension
that's pretty handy, actually. I'm not sure it should be a property of
the V spec itself, rather it could be a requirement that software
which is translated in this method could require an
that's pretty handy, actually. I'm not sure it should be a property of
the V spec itself, rather it could be a requirement that software
which is translated in this method could require an

By
Guy Lemieux
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#638
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Re: Smaller embedded version of the Vector extension
"...if written correctly" is precisely the point. If VLEN is specified as >=128, code that targets 128bits explicitly by setting VL to an appropriate constant for a large swath *is* correct. This
"...if written correctly" is precisely the point. If VLEN is specified as >=128, code that targets 128bits explicitly by setting VL to an appropriate constant for a large swath *is* correct. This

By
Zalman Stern
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#637
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Re: Smaller embedded version of the Vector extension
If the minimum VLEN is at least 128bits, one can translate NEON/SSE intrinsics directly without having to have every vector instruction dominated by a loop over the vector length.
Z
If the minimum VLEN is at least 128bits, one can translate NEON/SSE intrinsics directly without having to have every vector instruction dominated by a loop over the vector length.
Z

By
Zalman Stern
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#636
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Re: Smaller embedded version of the Vector extension
Krste, to be clear,The issue
The RVV spec should be inclusive, rather than exclusive. Setting VLEN
Sorry I wasn't clear. Of course, an implementation with VLEN=64 would
likely be slower than one
Krste, to be clear,The issue
The RVV spec should be inclusive, rather than exclusive. Setting VLEN
Sorry I wasn't clear. Of course, an implementation with VLEN=64 would
likely be slower than one

By
Guy Lemieux
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#635
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Re: Smaller embedded version of the Vector extension
Software should still work with VLEN>=64 if written correctly, as it should be VLEN agnostic.
Maybe it should be a recommendation that VLEN>=128, with a minimum of 64 for app processors?
Lower
Software should still work with VLEN>=64 if written correctly, as it should be VLEN agnostic.
Maybe it should be a recommendation that VLEN>=128, with a minimum of 64 for app processors?
Lower

By
Tony Cole
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#634
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Re: Smaller embedded version of the Vector extension
This is the requirement for app processors, which are not generally small cores.
Most competing SIMD extensions are at least 128b per vector register.
Lower performance on codes that work well on
This is the requirement for app processors, which are not generally small cores.
Most competing SIMD extensions are at least 128b per vector register.
Lower performance on codes that work well on

By
Krste Asanovic
·
#633
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Re: Smaller embedded version of the Vector extension
What is the advantage to RVV requiring VLEN >= 128?
I think this should be changed to VLEN >= 64 because:
1) VLEN = 64 is more likely for small implementations; creating a
mandatory expectation to
What is the advantage to RVV requiring VLEN >= 128?
I think this should be changed to VLEN >= 64 because:
1) VLEN = 64 is more likely for small implementations; creating a
mandatory expectation to

By
Guy Lemieux
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#632
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Re: Smaller embedded version of the Vector extension
see github issue #550
Krste
see github issue #550
Krste

By
Krste Asanovic
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#631
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Re: Smaller embedded version of the Vector extension
This is a good question.
So if the RVM22 profile requires VLEN=32, ELEN=64, LMUL=8 then the vector registers will have the same amount of state as ARM MVE.
Tariq
This is a good question.
So if the RVM22 profile requires VLEN=32, ELEN=64, LMUL=8 then the vector registers will have the same amount of state as ARM MVE.
Tariq

By
Tariq Kurd
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#630
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Re: 答复: [RISCV] [techvectorext] Smaller embedded version of the Vector extension
Hi, Krste:
The RISCV V TG have the plan to support a lowcost vector extension in RVMxx profile?
Best Regards
Shaofei
2021.6.3
邮件原件
发件人: krste@...
Hi, Krste:
The RISCV V TG have the plan to support a lowcost vector extension in RVMxx profile?
Best Regards
Shaofei
2021.6.3
邮件原件
发件人: krste@...

By
Shaofei (B)
·
#629
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Re: Smaller embedded version of the Vector extension
Hi Tony,
All of the vector permutation instructions can be simulated using the memory system. For example, vslide can be simulated by storing the vector register and loading it at an offset; vrgather
Hi Tony,
All of the vector permutation instructions can be simulated using the memory system. For example, vslide can be simulated by storing the vector register and loading it at an offset; vrgather

By
Nick Knight
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#628
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Re: Smaller embedded version of the Vector extension
Hi Bruce,
Do you mean vrgather instead of vslide?
I use vrgather_vx_* and vslidedown to perform a vector element rotate (and other things), see:
Hi Bruce,
Do you mean vrgather instead of vslide?
I use vrgather_vx_* and vslidedown to perform a vector element rotate (and other things), see:

By
Tony Cole
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#627
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Re: Smaller embedded version of the Vector extension
 could an extension just change state like the number of vector registers?

Don't understand tbis question  please elaborate.
Krste
 could an extension just change state like the number of vector registers?

Don't understand tbis question  please elaborate.
Krste

By
Krste Asanovic
·
#626
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Re: Smaller embedded version of the Vector extension
Thanks, I must have missed this bit:
"4.5. Mapping with LMUL > 1 and ELEN > VLEN
If vector registers are grouped to support larger SEW, with ELEN > VLEN, the vector registers in the group are
Thanks, I must have missed this bit:
"4.5. Mapping with LMUL > 1 and ELEN > VLEN
If vector registers are grouped to support larger SEW, with ELEN > VLEN, the vector registers in the group are

By
Tony Cole
·
#625
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Re: Smaller embedded version of the Vector extension
Section 4.5,
Krste
 On Wed, Jun 2, 2021 at 8:38 AM Andrew Waterman <andrew@...> wrote:
 It’s actually not fundamental to the ISA design that VLEN >= ELEN. An
 implementation with
Section 4.5,
Krste
 On Wed, Jun 2, 2021 at 8:38 AM Andrew Waterman <andrew@...> wrote:
 It’s actually not fundamental to the ISA design that VLEN >= ELEN. An
 implementation with

By
Krste Asanovic
·
#624
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Re: Smaller embedded version of the Vector extension
could an extension just change state like the number of vector registers?
could an extension just change state like the number of vector registers?

By
mark
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#623
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Re: Smaller embedded version of the Vector extension
We do allow supported SEW to vary with LMUL, so implementation can
support singlewidth operations on SEW=64. See section 4.5,
Krste
 So, (on a 32x 32bit vector register machine) the widening and
We do allow supported SEW to vary with LMUL, so implementation can
support singlewidth operations on SEW=64. See section 4.5,
Krste
 So, (on a 32x 32bit vector register machine) the widening and

By
Krste Asanovic
·
#622
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Re: Smaller embedded version of the Vector extension
The VLEN>=128 constraint is only for the application processor "V"
extension for the app profile  not for embedded vectors which can
have VLEN=32.
From spec Introduction:
'
The term base vector
The VLEN>=128 constraint is only for the application processor "V"
extension for the app profile  not for embedded vectors which can
have VLEN=32.
From spec Introduction:
'
The term base vector

By
Krste Asanovic
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#621
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Re: Smaller embedded version of the Vector extension
It seems that restriction of minimum LMUL=2 would be half number of vector registers and LMUL=4 would be 8 vector registers.
Thang
It seems that restriction of minimum LMUL=2 would be half number of vector registers and LMUL=4 would be 8 vector registers.
Thang

By
Thang Tran
·
#620
·
