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official v0.8 release of vector spec reference simulator

Krste, Roger We have just released an update of our free riscvOVPsim reference simulator version: 20191217.0 and put it on the https://github.com/riscv/riscv-ovpsim. riscvOVPsim supports the full

By Simon Davidmann Imperas · #1 ·

Calling Convention for Vector ?

Hi, Anyone know extra designed ABI information (like Calling Convention) about for vector register ? --Jojo

By "戎杰杰 · #2 ·

Re: Calling Convention for Vector ?

There is a brief sketch of the Linux vector calling convention here: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc Note this is the convention for normal C ABI calls; a

By andrew@... · #3 ·

Re: Calling Convention for Vector ?

Hi, Thanks for your mention. It’s so clear & simple, there is no convention for vector args & return of function ? also, according our long time designed cpu experiments, there should

By "戎杰杰 · #4 ·

Re: Calling Convention for Vector ?

Vectors are passed in memory and returned in memory. Vectors are arbitrary length, whereas the vector registers are fixed length, and can only be used to temporarily hold a portion of a memory vector.

By Earl Killian · #5 ·

Re: Calling Convention for Vector ?

Some code will not want args in vector regs, so that we don't have to save/restore them around calls. Some code will want args in vector regs, so that they can have subroutines that operate on

By Jim Wilson · #6 ·

Re: Calling Convention for Vector ?

Hi, We met some problems as your mention also. Consider some code will want args in vector regs, we study from SVE vregs layout and config our RISCV vregs layout as following: | v0-7

By "戎杰杰 · #7 ·

Re: Calling Convention for Vector ?

Providing callee-saved vector registers in the regular C calling convention might actually degrade performance, as most vector computation is done in leaf functions or in strip-mine loops that don't

By andrew@... · #8 ·

Re: Calling Convention for Vector ?

Oh, heck [*]: Callee saved registers of any form can have bad performance where there is a potential partial register issue. E.g. on an out of order machine with register renaming. Although even

By Andy Glew Si5 · #9 ·

Slidedown overlapping of dest and source regsiters

The slideup instruction has this restriction: The destination vector register group for vslideup cannot overlap the source vector register group or the mask register, otherwise an illegal instruction

By Thang Tran · #10 ·

Re: Slidedown overlapping of dest and source regsiters

It's important that the slidedown instruction can overwrite its source operand. Debuggers will use this feature to populate a vector register in-place without clobbering other architectural state.

By andrew@... · #11 ·

Re: Slidedown overlapping of dest and source regsiters

Hi Andrew, I do not understand your statement. Why is it important? Why is the difference with slideup? The slideup cannot clobber the source operand with destination operand because the

By Thang Tran · #12 ·

Re: Slidedown overlapping of dest and source regsiters

Hi Thang, I think Andrew is suggesting that the vslideup restriction is there to allow some flexibility with implementations. However, one of (vslideup/vslidedown) needs to allow the same source/dest

By Guy Lemieux · #13 ·

Re: Slidedown overlapping of dest and source regsiters

Thanks Guy for the explanation, but my implementation is both incrementing element index for slideup and decrementing element index for slidedown (which is symmetrical implementation and simplest from

By Thang Tran · #14 ·

Re: Slidedown overlapping of dest and source regsiters

I'm curious why you chose to be symmetrical (no need), and why you decided incrementing for slideup decrementing for slidedn (I would do the opposite). By incrementing for vslidedown, and

By Guy Lemieux · #15 ·

Re: Slidedown overlapping of dest and source regsiters

Oops, yes, I meant vslide1down. Using vslide1down isn't about performance; it's the only way I know of for the debugger to construct a vector without additional storage. The alternative would have

By andrew@... · #16 ·

Minutes from 2020/1/24 meeting

Date: 2020/1/24 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~20 github: https://github.com/riscv/riscv-v-spec Outstanding items from prior meeting: #362/#354, #341,

By Krste Asanovic · #17 ·

RISC-V Vector Task Group: fractional LMUL

In the last meeting, we discussed a problem that would be introduced if we were to drop the fixed-size (b/h/w) variants of the vector load/stores and only have the SEW-size (e) variants. From

By Krste Asanovic · #18 ·

Re: RISC-V Vector Task Group: fractional LMUL

Could a fractional LMUL circumvent the constraint that a widening instruction's output register group must be larger than its input register group(s)? --Nick Knight

By Nick Knight · #19 ·

Re: RISC-V Vector Task Group: fractional LMUL

I'm realizing the idea doesn't quite work unless machine actually stores the fractional LMUL value (to cope with SLEN and widening instruction behavior), and so would need the new instruction and

By Krste Asanovic · #20 ·

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