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This observation is a bit of a memory side issue but is tied to vector indexed loading semantics. The problem that I see is that my address offsets in the vector indexed load instruction are rather

By Nagendra Gulur · #41 ·

Re: Vector Indexed Loads - Partial Return?

Since this is happening to an already-slow memory access, I would guess performing checks in software would be the better way to go. There is no current talk about aborting a long-running indexed

By Guy Lemieux · #42 ·

Re: Vector Indexed Loads - Partial Return?

Anecdote: One of my initial inspirations for working on dynamic out of order scheduling was to support incremental time pipeline vectors, both scatter/gather and stride. I.e. the P6 RS began

By Andy Glew Si5 · #43 ·

Re: 64-bit instruction encoding wish list

Hi all, I am not sure if these require 64-bit encoding, but I am interested in extended data types, especially signed-integer-complex, single-precision floating-point complex, and unums.

By Richard Newell · #44 ·

Re: 64-bit instruction encoding wish list

My current "long instruction encoding" proposal has an example encoding for 64-bit V extension

By Claire Wolf <claire@...> · #45 ·

Re: 64-bit instruction encoding wish list

It appears I can not edit the wiki. But I can clarify one item. Regarding "Indexed memory accesses that implicitly scale the index by SEW/8": Explanation: In scientific sparse matrix codes (and

By Nagendra Gulur · #46 ·

Re: 64-bit instruction encoding wish list

regarding vector reduction destination: the V spec seems to allow for really large vector machines with thousands of vector elements. I'm not sure what the right bit width for the field with the

By Claire Wolf <claire@...> · #47 ·

Re: 64-bit instruction encoding wish list

How about if the destination element number came from a scalar register? So we will need only 5 bits to specify the x register. This may even work better than hard coding the destination inside the

By Nagendra Gulur · #48 ·

Re: 64-bit instruction encoding wish list

to me it seems like reading the dest element index from a scalar reg sounds like a significant microarchitectural overhead. can you describe why this is needed? I would assume that use cases for this

By Claire Wolf <claire@...> · #49 ·

Re: 64-bit instruction encoding wish list

Open to feedback here.. But my thought was that I will not need vslide1up if I am able to control the reduction destination. A loop around the instructions: vredsum vd[rs1], vs1[rs1], vs2[*] rs1 = rs1

By Nagendra Gulur · #50 ·

Re: 64-bit instruction encoding wish list

my response below is now off-topic, and covers the more flexible reductions wanted by Nagendra. i discourage any further followups here (instead, please search for another recent series of posts

By Guy Lemieux · #51 ·

Re: issue #393 - Towards a simple fractional LMUL design.

My apologies, especially to those who have sent some feedback. I had thought I had already sent this second iteration (It has been on git hub issue since Monday. A slightly

By David Horner · #52 ·

issue #393.3 - Towards a simple fractional LMUL design - third itteration .

I am sending out the partial description of the next itteration for the Simple Fractioanl LMUL design. It is incomplete because I only recently clarified in my own mind a means to

By David Horner · #53 ·

issue #393.4 - Towards a simple fractional LMUL design - third itteration .

This is the fourth installation of the Simple Fractioanl LMUL design. It does not yet address SLEN and a suggestion for a fractional SLEN (fracSLEN). It should however clarify the

By David Horner · #54 ·

Meeting happening today

I neglected to send an earlier reminder, but the vector TG meeting will be happening today per member calendar details, Krste

By Krste Asanovic · #55 ·

Fractional LMUL Constraint

Maybe this has been stated already, and I just haven't seen it, but it seems like there's a constraint with fractional LMUL that wasn't there before. The compiler must ensure that: LMUL >=

By Bill Huffman · #56 ·

Re: Fractional LMUL Constraint

Intriguing. I especially appreciate the effort to identify fundamental aspects of fractional LMUL. On 2020-03-21 3:46 p.m., Bill Huffman wrote: As you mention

By David Horner · #57 ·

Minutes of 2020/3/20 vector TG meeting

Date: 2020/3/20 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #367, #393 The following

By Krste Asanovic · #58 ·

Re: Minutes of 2020/3/20 vector TG meeting

... I assume that: ELEN=64b here. It can't be smaller because SEW=64b is listed. It can't be larger because SLEN=64b LMUL=1/8, SEW=32b is illegal LMUL=1/4, SEW=64b is illegal LMUL=1/8,

By Bill Huffman · #59 ·

Re: Fractional LMUL Constraint

I agree, this is a useful and acceptable constraint. I proposed it in a different but equivalent formulation (SEW <= ELEN / n when LMUL = 1/n) in response to a previous fractional LMUL proposal by

By Robin Kruppe <hanna.kruppe@...> · #60 ·

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